• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.431-435
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• 2011

This paper presents optimized searching technique to improve the performance of H.264/AVC. The proposed CAVLC encoder uses forward and backward searching algorithm to compute the parameters. By zero-block skipping technique and pipelined scheduling, the proposed CAVLC encoder can obtain better performance. The experimental result shows that the proposed architecture needs only 66.6 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 13.8% than that of previous designs. The proposed CAVLC encoder was implemented using VerilogHDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 15.6K with 125Mhz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.61-70
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• 2005

In this paper, we propose an efficient global placement algorithm which is an enhanced version of Hybrid Placer$^{[25]}$, a standard cell placement tool, which uses a middle-down approach. Combining techniques used in the well-known partitioner hMETIS and the RBLS(Relaxation Based Local Search) in Hybrid Placer improves the quality of global placements. Partitioning techniques of hMETIS is applied in a top-down manner and RBLS is used in each level of the top-down hierarchy to improve the global placement. The proposed new approach resolves the problem that Hybrid Placer seriously depends on initial placements and it speeds up without deteriorating the placement quality. Experimental results prove that solutions generated by the proposed method on the MCNC benchmarks are comparable to those by FengShui which is a well known placement tool. Compared to the results of the original Hybrid Placer, new method is 5 times faster on average and shows improvement on bigger circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.113-122
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• 2010

In this paper, we propose a CP (Cyclic Prefix) detection based SSS (Secondary Synchronization Signal) detection method for initial cell search in 3GPP LTE (3rd Generation Partnership Project Long Term Evolution) FDD/TDD (Frequency Division Duplex/Time Division Duplex) dual mode downlink receiver. In general, a blind coherent SSS detection method which can detect SSS without CP detection is applied. However, coherent detection method caused performance degradation by channel compensation error at high speed environment because it uses estimated CFR (Channel Frequency Response) at PSS (Primary Synchronization Signal), and it can be more serious problem in TDD mode due to increased distance between PSS and SSS. Also blind detectionhas the drawback of high computational complexity. Therefore, we proposed a CP type pre-decision structure with non-coherent SSS detection which has stable operation in high speed channel environments for 3GPP LTE TDD mode as well as FDD mode, and can reduce computational complexity by applying CP detection before SSS detection. Simulation results show that the proposed method has stable operation for 3GPP LTE TDD/FDD dual mode downlink receiver in various channel environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.302-313
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• 2010

In this paper, we propose an enhanced AGC (Automatic Gain Control) structure and P-SCH detection method for initial cell search in 3GPP (3rdGenerationPartnershipProject) LTE (Long Term Evolution) FDD(Frequency Division Duplex) / TDD (Time Division Duplex) dual mode system. Since TDD frame structure consists of uplink subframe and downlink subframe, conventional AGC structure causes P-SCH detection performance degradation by increase of AGC variation due to signal power difference between uplink and downlink subframe. Also, P-SCH detection performance is degraded by distortion of P-SCH correlation characteristic in frequency offset and multipath fading channel environments. Therefore, we propose an AGC structure which can minimize P-SCH detection performance degradation with stable operation in 3GPP LTE TDD mode as well as FDD mode. Also we propose a P-SCH detection method which can reduce distortion of correlation chareteristics in frequency offset and multipath fading environments and obtain good P-SCH detection performance. Simulation results show that the proposed AGC structure and P-SCH detection method have stable AGC operation and excellent P-SCH detection performance for 3GPP LTE TDD / FDD dual mode downlink receiver in various channel environments.

• Journal of Korea Spatial Information System Society
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• v.9 no.1
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• pp.1-13
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• 2007

The necessity of future index is increasing to predict the future location of moving objects promptly for various location-based services. A representative research topic related to future index is the probability trajectory prediction technique that improves reliability using the past trajectory information of moving objects in the road network environment. However, the prediction performance of this technique is lowered by the heavy load of extensive future trajectory search in long-range future queries, and its index maintenance cost is high due to the frequent update of future trajectory. Thus, this paper proposes the Probability Cell Trajectory-Tree (PCT-Tree), a cell-based future indexing technique for efficient long-range future location prediction. The PCT-Tree reduces the size of index by rebuilding the probability of extensive past trajectories in the unit of cell, and improves the prediction performance of long-range future queries. In addition, it predicts reliable future trajectories using information on past trajectories and, by doing so, minimizes the cost of communication resulting from errors in future trajectory prediction and the cost of index rebuilding for updating future trajectories. Through experiment, we proved the superiority of the PCT-Tree over existing indexing techniques in the performance of long-range future queries.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.10
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• pp.593-602
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• 2004

A new surface reconstruction scheme for approximating the surface from a set of unorganized 3D points is proposed. Our method, called shrink-wrapped boundary face (SWBF) algorithm, produces the final surface by iteratively shrinking the initial mesh generated from the definition of the boundary faces. Proposed method surmounts the genus-0 spherical topology restriction of previous shrink-wrapping based mesh generation technique, and can be applicable to any kind of surface topology. Furthermore, SWBF is much faster than the previous one since it requires only local nearest-point-search in the shrinking process. According to experiments, it is proved to be very robust and efficient for mesh generation from unorganized points cloud.

• Journal of KIISE
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• v.44 no.6
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• pp.573-580
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• 2017

Despite the recent remarkable advances in the computing power of mobile devices, the heat and battery problems still restrict their performances, particularly compared to PCs. Therefore, in the application of the ray-tracing technique for high-quality rendering, the consideration of a method that traces only the secondary rays while the effects of the primary rays are generated through rasterization-based OpenGL ES rendering is worthwhile. Given that most of the rendering time is for the secondary-ray processing in such a method, a new volume-grid technique for dynamic scenes that enhances the tracing performance of the secondary rays with a low coherence is proposed here. The proposed method attempts to model all of the possible spatial secondary rays in a fixed number of sampling rays, thereby alleviating the visitation problem regarding all of the cells along the ray in a uniform grid. Also, a hybrid rendering pipeline that speeds up the overall rendering performance by exploiting the mobile-device CPU and GPU is presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.635-637
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• 2013

This paper proposed a new hardware architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA environment, and has the performance of 813fps in case of the search range of 64 pixels and the image size of $640{\times}480$.