• Proceedings of the KAIS Fall Conference
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• 2007.11a
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• pp.140-143
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• 2007

본 연구의 목적은 반도체 후공정 제조 시스템인 Screen Printer시스템에서의 프린팅 공정시 프린팅에 사용되는 Mesh Mask, Urethane Blade의 재질이 사용되는 반복횟수의 증가에 따라 재질의 변화에 의한 문제점과 프린팅 공정 파라미터인 Table 접촉거리, Squeegee 하강위치의 주변환경에 의한 변화를 보상하여 일정하게 프린팅이 될 수 있는 시스템을 구현 하는데 목적이 있으며, 이 논문은 서보모터를 구동하는 위치제어 시스템에 로드셀（Loadcell）을 이용하는 압력제어시스템을 연구하고 구현하고자 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.385-388
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• 2004

염료감응형 태양전지는 다공질 $TiO_2$ 전극막, 광감응형 염료, 전해질, 상대전극으로 구성된, 전기화학적 원리를 응용한 신형태양전지이다. 본 연구에서는 백금 상대전극의 제조 방법에 따른 태양전지의 효율 및 특성을 비교하였다. 본 연구에 사용된 백금 상대전극막의 제조 방법은 스퍼터링(sputtering)법 과 전기도금(electroplating)법이다. 두 상대전극의 전기화학적 특성은 cyclic voltammetry와 Imepedance spectroscopy 측정을 통하여 비교하였다. 두 전극이 태양전지의 효율 및 특성에 미치는 영향은 단위 셀 태양전지를 제조하여 단파장 하에서 $350nm{\sim}700nm$의 파장별 효율을 측정함으로써 조사하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.5
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• pp.31-37
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• 2017

In this Paper, we have Improved the Manufacturing Process of Liquid Aluminum Sulfate using the Design of Automated Measurement Systems. The Manufacturing Process of Liquid Aluminum Sulfate uses a Large Weight. The Quality of a Product Depends Highly on the Proportion of the Raw Material Input in the Production Process. Therefore, it is Very Important to Accurately Measure the Amount of Raw Material. For Automation Design, Load Cell Sensor which can Measure Large Weight Accurately and PLC Technology which is most used in Automation Process are Applied. The Content of Aluminum Oxide in the Aluminum Sulfate Produced before the Automation Design Varies from 8.023% to 8.250%. However, after Automation Design, the Amount of Change from 8.09% to 8.19% was Greatly Reduced. As a Result, we could Reduce the Quality Defect rate Due to Weighing Errors and Reduce Safety Accidents by Applying Automation System.

• Journal of the Korean Electrochemical Society
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• v.22 no.2
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• pp.60-68
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• 2019

High-voltage operation of the lithium ion battery is one of the advantageous approaches to obtain high energy capacity without changing the conventional cell components and structure. However, operating at harsh condition inevitably results in severe side reactions at the electrode surface and structural disintegration of active material particles. Herein we coated layers composed of $Al_2O_3$ and ZnO on the electrode based on NCM using atomic layer deposition (ALD). Thicker layers of novel Al-doped ZnO (AZO) coating compared to conventional ALD coated layers are prepared. Cathode based on NCM with the varying AZO coating thickness are fabricated and used for coin cell assembly. Effect of ALD coating thickness on the charge-discharge cycle behavior obtained at high-voltage operation was investigated.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.791-796
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• 2017

In this study, we investigated the influence of the fabrication process of stacked capacitors on the cell capacitance by using Load Lock (L/L) LPCVD system for dielectric thin film of DRAM capacitor. As a result, it was confirmed that the capacitance difference of about 3-4 fF is obtained by reducing the effective thickness of the oxide film by about $6{\AA}$ compared to the conventional non-L/L device. In addition, Cs was found to be about 3-6 fF lower than the calculated value, even though the measurement range of the thickness of the nitride film as an insulating film was in a normal management range. This is because the node poly FI CD is managed at the upper limit of the spec, resulting in a decrease in cell surface area, which indicates a Cs reduction of about 2fF. Therefore, it is necessary to control the thickness of insulating film and CD management within 10% of the spec center value in order to secure stable Cs.

• 전자공학회논문지 IE
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• v.48 no.2
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• pp.6-11
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• 2011

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor's parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process($0.11{\mu}m$, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.

• Journal of the Korean Electrochemical Society
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• v.2 no.4
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• pp.202-208
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• 1999

Composite cathodes of $50/50\;vol\%$ LSM-YSZ $(La_{-x}Sr_xMnO_3-yttria\;stabilized\;zirconia)$ were deposited onto dense YSZ electrolytes by colloidal deposition technique. The cathode characteristics were then examined by scanning electron microscopy (SEM) and studied by ac-impedance spectroscopy (IS). The conditioning effects on LSM-YSZ cathodes were seen and remedies for these effects were noted in order to improve the performance of a solid oxide fuel cell (SOFC). The effects of temperature on impedance, surface contamination on cathode bonding to YSZ electrolyte, changing Pt paste, aerosol spray technique applied to curved surface on microstructure and cell to cell variability were solved by testing at $900^{\circ}C$, sanding the YSZ surface, using only one batch of Pt paste, using flat YSZ plates and using consistent procedures and techniques, respectively. And then, reproducible impedance spectra were confirmed by using the improved cell and the typical spectra measured for an (air)LSM-YSZ/YSZ/LSM-YSZ(air) cell at $900^{\circ}C$ were composed of two depressed arcs. Impedance characteristics of the LSM-YSZ cathodes were also affected by experimental conditions such as catalytic interlayer, composite cathode compositions and applied current.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.409-409
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• 2010

솔라셀은 차세대 대체 에너지 소스로 최근 큰 각광을 받고 있다. 솔라셀의 제조에 있어 가장 중요한 공정은 마이크로 결정질 및 비결정질 실리콘(uC-Si:H and a-Si:H) 박막을 증착하는 PECVD (Plasma Enhanced CVD)공정이다. 현재까지 이 증착공정을 위한 플라즈마 소스로 CCP(Capacitively Coupled Plasma)가 주로 사용되어 왔다. 그러나, CCP를 플라즈마 소스를 사용한 경우 솔라셀 대량 생산 적용시 다른 방법들에 비해 긴 공정 시간이 해결해야 할 문제점으로 대두되었다. 본 발표에서는 솔라셀의 대량 생산을 위한 마이크로 결정질 실리콘 박막 증착에 있어 현 시점에서 해결되어야 할 문제점에 대해 고찰해 보고자 한다. 현재까지 이러한 문제점들을 해결하기 위해 적용되어 왔던 플라즈마 소스들을 나열하고 이러한 플라즈마 소스에 대한 특성 및 문제점들을 고찰한다. 또한, PECVD 공정상의 문제점을 해결하기 위한 플라즈마 조건을 플라즈마 벌크에서의 전자에너지 분포를 기준으로 제시하고자 한다. 솔라셀용 결정질 실리콘 박막 증착용 플라즈마 소스로 hollow cathode 방전이 가장 유력시되고 있다. 본 연구에서는 CCP 플라즈마에서 hollow cathode 방전시 발생되는 플라즈마 특성에 대한 기초 연구를 제시한다. 기초 연구를 위해 다양한 불활성 가스인 아르콘, 헬륨, 크립톤 가스에 13.56 MHz의 RF 파워를 인가하고 방전되는 플라즈마 밀도 변화를 관찰하였다. 특히, 다양한 hole diameter에서 발생되는 플라즈마 밀도의 변화를 기존 평면 CCP 플라즈마의 밀도에 비교하여 분석함으로써 hole diameter에 따른 효과를 관찰하였다. 이러한 결과는 PIC 시뮬레이션을 통해 얻은 전자에너지 분포함수를 바탕으로 메커니즘을 논의하고자 한다. 마지막으로 솔라셀용 PECVD공정을 위해 고밀도 플라즈마 소스의 필요성뿐 만 아니라 대면적 소스의 구현에 대한 문제점을 고찰하였다. 대면적 공정에서 가장 중요한 핵심 연구 이슈는 공정 균일도를 높이는 것이다. CCP 플라즈마 소스에서 전극의 크기가 대면적화 됨에 따라 발생되는 전자기파 효과에 의한 불균일도에 대해 RF 전자기장 시뮬레이션을 통해 확인하고, 균일도 확보를 위한 방안에 대한 논의하고자 한다.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.106.2-106.2
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• 2011

다층 박막 구조로 이루어진 CdS/CdTe 태양전지의 경우, 각각의 박막이 다양한 제조 공정을 거치면서 물성특성의 변화를 겪게 된다. 각각의 박막이 고온의 열처리 공정과, $CdCl_2$ 용액 처리 및 후면 산화막 제거 공정 등을 거치게 되면서 겪게 되는 물성 변화 분석을 살펴보고자 한다. 각각의 박막 제조 방식은 일반적으로 사용되는 방식으로, CdS의 경우는 용액성장법(Chemical Bath Deposition, CBD), CdTe의 경우는 근접승화법(Closed Space Sublimaition, CSS)을 사용했으며, X-Ray Diffractometer (XRD), Raman spectroscopy, Field Emission Scanning Electron Microscope (FE-SEM), Energy Dispersive Spectroscopy (EDS), X-ray Photoelectron Spectroscopy (XPS) 등을 이용하여 분석하였다. 각각의 셀 제조 공정을 거치면서 CdS, CdTe 박막들은 결정, 광 특성, 성분 변화를 보였다.

• Applied Chemistry for Engineering
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• v.32 no.6
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• pp.599-606
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• 2021

In this study, an experiment and a reaction characteristic study were conducted to enhance the reaction activity of V₂O₅/WO₃/TiO₂ at 300 ℃ or less by adding selenium to the support, in a selective catalytic reduction method using ammonia as a reducing agent to remove nitrogen oxides. Se-TiO₂ and TiO₂ were synthesized using the sol-gel method, and used as a support when preparing V₂O₅/WO₃/TiO₂ and V₂O₅/WO₃/Se-TiO₂ catalysts. The reaction activity of our catalyst was compared with that of a commercial catalyst. The denitration efficiency of the catalyst using TiO₂ prepared by the sol-gel method was lower than that of the catalyst prepared using commercial TiO₂, but was improved by the addition of selenium. Thus, the effect of selenium addition on the catalyst structure was analyzed using BET, XRD, Raman, H₂-TPR, and FT-IR measurements and the effect of the increase in specific surface area by selenium addition and the formation of monomer and complex vanadium species on reaction characteristics were confirmed.