• Journal of Digital Convergence
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• v.10 no.11
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• pp.371-376
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• 2012

In this paper, we propose a new data coding method and its circuits for minimizing data transition in text image. The proposed circuits can solve the synchronization problem between input data and output data in the modified LVDS algorithm. And the proposed algorithm is allowed to transmit two data signals through additional serial data coding method in order to minimize the data transition in text image and can reduce the operating frequency to a half. Thus, we can solve EMI(Electro-Magnetic Interface) problem and reduce the power consumption. The simulation results show that the proposed algorithm and circuits can provide an enhanced data transition minimization in text image and solve the synchronization problem between input data and output data.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.3
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• pp.623-630
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• 2016

Heterogeneous IoT devices must satisfy a certain level of security for mutual connections and communications. However, a performance degradation of cryptographic algorithms in resource constrained devices is inevitable and so an optimization or efficient implementation method is necessary. In this paper, we study an efficient implementation method for rotation operations regarding registers for running ARX lightweight block ciphers. In a practical sense, we investigate the performance of modified rotation operations through experiments using real experiment devices. We show the improved performance of modified rotation operations and discover the significant difference in measured performance between simulations and real experiments, particularly for 16-bit MSP microcontrollers.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.4
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• pp.442-449
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• 2002

EZW (Embedded Zerotree Wavelet) is an efficient algorithm to encode wavelet-transformed image. In this algorithm, each coefficient of wavelet transformed image is given one of the specific symbols and encoded according to its significant priority. In this paper, we analysis the occurrence conditions of symbols in EZW and propose a modified EZW algorithm. In the proposed algorithm, the significance of an IZ (Isolated Zero) symbol is determined by the additional conditions as well as its absolute value. The occurrence of IZ symbols is decreased and the required bits for insignificant IZ symbols is saved, so we obtained good quality of the reconstructed image.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2007.02a
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• pp.87-90
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• 2007

기존의 Steganography는 정보를 숨김에 있어 히스토그램을 shifting 하거나 픽셀간의 상관관계를 변형하는 등 다양한 방식이 제안되었다. 그런 논문들이 가지고 있던 용량적 한계를 일부 극복하고, PSNR을 고려하여 새로운 방식을 제안한다. 소개하는 기술은 두 색깔을 파트너로 맺어, 숨김 비트에 따라 서로 파트너로 바뀌도록 설계되었다. 숨긴 용량의 크기와PSNR의 변화를 실험 결과에서 볼 수 있으며, 이는 기존 논문과의 비교를 통해 효율성이 입증된다.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.1
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• pp.69-75
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• 2014

Audio seganography is the art and science of writing hidden messages that evolves as a new secret communication method. And audio steganography is similar to the process of modifying the Least Significant Bit of image files 8th LSB layer embedding has been done for desired binary messages. The effective of steganographic tools is to obtain imperceptible and robust way to conceal high rate of secret data. The objective of this paper is to propose a method for hiding the secret messages in safer manner from external attacks by modified LSB technique and encryption rearrangement key.

• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.3
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• pp.336-341
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• 2014

When using a higher-order modulation scheme, there are variations in bit-reliability depending on the bit position in a modulation symbol. Variations of bit-reliability in the codeword block lower the decoding performance. Also, the decoding performance increases as the sum of the bit-reliabilities in the codeword block increases. This paper presents a novel hybrid automatic repeat request scheme that increases the sum of the reliabilities of the transmitted bits by lowering the modulation order, and decreases the variations of bit-reliability in the codeword block by preferentially retransmitting bits with low reliability. The proposed scheme outperforms the constellation rearrangement scheme. Furthermore, the proposed scheme also provides a good solution in cases where the size of the retransmission block is smaller than the size of the initial transmission block.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.439-442
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• 2009

본 연구는 16 비트 CPU를 위한 새로운 C 컴파일러를 개발하고자 한다. 새로운 ASIC 프로세서가 특정 용도로 설계되었을 때 그 CPU를 위한 새로운 컴파일러의 개발이 필요하다. 공개 소프트웨어인 GNU C 컴파일러를 사용하여 기계 의존 원시 파일들을 수정함으로서 새로운 컴파일러를 개발할 수 있다. 개발된 컴파일러는 단지 기계어에 의해 처리될 수 있는 기능들만 지원할 수 있기 때문에 곱 셈, 나눗셈, 부동소수점 처리등과 같은 기능들을 지원하기 위해서는 더 많은 연구가 필요하다. 완전한 컴파일러가 개발된 후에는 새로운 CPU에서 실행될 수 있는 응용 프로그램의 개발이 필요하다. 본 연구에 의해서 앞으로 개발될 여러 가지 다른 용도의 CPU를 위한 컴파일러들이 쉽게 개발될 수 있을 것이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.7C
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• pp.540-547
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• 2008

In this paper, we proposed a new VLSI architecture which can generate computer-generated hologram (CGH) in real-time and implemented to hardware. The modified algorithm for high-performance CGH was introduced and re-analyzed (or designing hardware. from both numerical and visual analysis, the infernal number system of hardware was decided. CGH algorithm and precision analysis enabled to propose a new cell architecture for CGH. The operational sequence was analyzed with the architecture of CGH cell and the characteristics of the modified CGH algorithm, and finally the pipelined architecture and the operational timing were proposed.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10a
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• pp.667-670
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• 2001

인터넷 정보가전분야에 적용되는 내장형 리눅스 시스템은 제어장치, 휴대형 단말기나 홈서버등 용도에 따라 시간 제한과 관련한 서비스를 지원해야 하므로 실시간성을 가져야 한다. 그러나, 현재 적용되고 있는 대부분의 내장형 리눅스(Embedded Linux) 시스템은 표준 리눅스 시스템을 참조하여 구축되어, 리눅스의 스케줄링 구조에 따라 실시간 태스크라 할지라도 작업 수행시간에 대한 예측성(Predictability)이 떨어져 실시간성을 보장할 수 없다. 본 연구는 리눅스의 스케줄링 기법을 비트맵(Bitmap)을 이용한 기법으로 수정하여 실시간 태스크들에 대한 고정 스케줄링 시간을 갖는 스케줄러(scheduler)를 구현했으며, 시뮬레이션을 통한 표준 리눅스 스케줄러와 구현된 스케줄러의 비교 자료를 제시했다.