• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.6
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• pp.1295-1305
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• 2017

There is SEED cryptosystem in domestic block cipher standard. This code was drafted by the Korea Information Security Agency (KISA) in October 1998 and underwent a public verification process in December of the same year, which resulted in the final amendment to improve safety and performance. Unlike DES, it is a 128-bit block cipher that has been passed through various processes and established in 2005 as an international standard. It is a block cipher with a pastel structure like DES, but the input bit block has been increased to 128 bits, double DES. In this paper, first, we introduce the general algorithm of SEED cryptosystem and analyzed mathematically generating principle of key-value which is used in F-function. Secondly, we developed a table that calculates the exponent of the primitive element ${\alpha}$ corresponding to the 8-bit input value of the S-function and finally analyzed calculating principle of S-function designed in G-function through the new theorem and example. Through this course, we hope that it is to be suggest the ideas and background theory needed in developing new cryptosystem to cover the weakness of SEED cryptosystem.

• Journal of Internet Computing and Services
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• v.4 no.4
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• pp.9-14
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• 2003

A GUI (graphical user interface) has been a dominant platform for HCI (human computer interaction). A GUI - based interaction has made computers simpler and easier to use. The GUI - based interaction, however, does not easily support the range of interaction necessary to meet users' needs that are natural. intuitive, and adaptive. In this paper, the modified BMA (block matching algorithm) is proposed to track a hand in a sequence of an image and to recognize it in each video frame in order to replace a mouse with a pointing device for a virtual reality. The HCI system with 30 frames per second is realized in this paper. The modified BMA is proposed to estimate a position of the hand and segmentation with an orientation of motion and a color distribution of the hand region for real - time processing. The experimental result shows that the modified BMA with the YCbCr (luminance Y, component blue, component red) color coordinate guarantees the real - time processing and the recognition rate. The hand tracking by the modified BMA can be applied to a virtual reclity or a game or an HCI system for the disable.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.409-416
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• 2024

With the expansion of floating-point operation requirements for fast high-speed data signal processing and logic operations, the speed of the floating-point operation unit is the key to affect system operation. This paper studies the performance characteristics of different floating-point multiplier schemes, completes partial product compression in the form of carry and sum, and then uses a carry look-ahead adder to obtain the result. Intel Quartus II CAD tool is used for describing Verilog HDL and evaluating performance results of the floating point multipliers. Floating point multipliers are analyzed and compared based on area, speed, and power consumption. The FMAX of modified Booth encoding with Wallace tree is 33.96 Mhz, which is 2.04 times faster than the booth encoding, 1.62 times faster than the modified booth encoding, 1.04 times faster than the booth encoding with wallace tree. Furthermore, compared to modified booth encoding, the area of modified booth encoding with wallace tree is reduced by 24.88%, and power consumption of that is reduced by 2.5%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1267-1275
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• 2017

This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over $GF(2^{233})$, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.11
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• pp.19-29
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• 2001

The Pan-European Digital Audio Broadcasting(DAH) system's performance is characterized and improved with the aid of turbo codec. From the fact that the first bit among the four coded bits at the RCPC coding defined in the Eureka 147 DAD system is not. punctured and always transmitted, this paper proposes a new turbo coded DAB system model that replaces the existing RCPC codec by a turbo codec without modifying the puncturing procedure and puncturing vectors defined in the standard DAB system for compatibility. The performance of a new system is compared to that of the conventional system under the Rician fading channel and the Rayleigh fading channel in conjunction with DAD transmission mode I and III suitable for the terrestrial single frequency network and satellite broadcasting.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.27-32
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• 2021

This paper proposes an energy-efficient cache and memory management scheme for next-generation IoT devices. The proposed scheme adopts a low-power phase-change memory (PCM) as the main memory of IoT devices, aims at minimizing the write traffic to PCM, which is vulnerable to write operations. Specifically, when a cache block of the last-level cache memory is flushed to main memory, the cache block that causes less writes to PCM is preferentially replaced by tracking the modifications of each cache line that constitutes the cache block. In addition, by considering the reference bit of the cache block and the dirty bit of the cache lines, our scheme reduces the energy consumption without degrading the memory system performances. Through simulations using SPEC benchmarks, it is shown that the proposed scheme reduces the write traffic to PCM by 34.6% on average and the power consumption by 28.9%, without memory performance degradations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2081-2093
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• 1994

In this study, we design and implement 64 QAM demodulator which has 155 Mbps, first level of CCITT G707 SDH(Synchronous Digital Hierachy) for STM 1 signal transmission. Carrier recovery which effects the demodulator performance uses decision feedback carrier using 8 bits A/D converter. Also, PSF(Pulse Shaping Filter) is 7 order elliptic filter. Carrier recovery circuit is designed and implemented digital type which use high 3 bits of 8 bits conversion data as data and the order low bits as error data and hybrid type which use VCO and analog integrator. Therefore we obtain stable performance recovery.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.785-792
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• 2004

In this paper, we propose a fast and efficient method that improves the performance of embedded zerotree wavelet(EZW) algorithm introduced by Sharipo． In the EZW algorithm, two bits are allocated for a symbol, but it is inefficient for compression and the zerotree coding wastes much time at encoding. In this paper, in order to increase the efficiency of compression, it will be allocated a variable bit for a symbol at each subband. To reduce the encoding time, we use a backscan method and lifting scheme instead of filter bank in wavelet transform. Experimental result are shown that the algorithm suggested in this paper has a better performance about 0.3∼1.5㏈ PSNR while the encoding time was speeded up more than 2-10 times compared with the EZW algorithm.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.06a
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• pp.197-200
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• 2017

퍼지 논리를 기반으로 한 적응형 스트리밍 기법인 FDASH 적응 알고리즘은 빠르게 변하는 네트워크 상황에서 우수한 콘텐츠의 화질을 보장하면서 끊김 없는 서비스를 제공하는 특성을 보이지만 비디오의 화질이 자주 변하기 때문에 최고의 사용자 체감 품질 (QoE: Quality of Experience)을 제공하지 못 할 수도 있다. 본 논문에서는 제한된 버퍼 크기를 가지고 동일한 콘텐츠의 화질을 보장하면서도 비디오 화질의 변화 횟수를 줄여서 최적의 QoE를 제공할 수 있도록 하는 변환된 퍼지 논리 기반의 DASH 적응 알고리즘을 제안하고자 한다. 제안된 방식은 우선 퍼지 논리 제어부(FLC : Fuzzy Logic Controller)의 수정을 통하여 다음 세그먼트의 비트율에 대해 최적의 판단을 하도록 하였고, 세그먼트 비트율 필터링 모듈 (SBFM: Segment Bitrate Filtering Module)을 추가하여 비디오 화질의 변화 횟수가 최소화 될 수 있도록 하였으며, 스트리밍 서비스 시작 시 SBFM에 의해 일정시간 저화질의 비디오를 시청해야 하는 상황을 막기 위한 Start Mechanism을 추가하였고, 마지막으로 버퍼의 오버플로우를 방지하기 위해 Sleeping Mechanism을 추가하였다. NS-3를 이용한 네트워크 모의실험 결과를 통해 제안된 방식이 FDASH 방식에 비하여 제한된 버퍼크기 상황 하에서도 오버플로우가 발생하지 않으며 점대점(Point to Point) 상황에서는 거의 동일 화질 성능을 보이면서도 비디오 화질 변화 횟수를 50% 이상 줄일 수 있음과 일반 Wifi환경에서는 오히려 17.8%정도 더 뛰어난 비디오 화질 성능을 보이면서 비디오 화질변화 횟수 측면에서는 53.1%정도 줄일 수 있음을 보여준다.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1329-1336
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• 1996

In many image compression applications, the discrete cosine transform (DCY) is well known for is highly efficient coding performance. However, it produces undesirable block artifacts in low-bit rate coding. In addition, in many practical applications, faster computation and easier VLST implementation of DCT coefficients are also important issues. The removal of the block artifacts and faster DCT computation are therefor of practical interest. In this paper, a modified DCTcomputation scheme was investigated, which provides a simple efficient solution to the reduction of the block artifacts while achieving faster computation. We have applied the new ap-proach to the low-bit rate coding and decoding of images. Simulation results on real images have verified the improved performance of the proposed method over the standar d method.