• Journal of the Institute of Convergence Signal Processing
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• v.3 no.2
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• pp.53-57
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• 2002

Recently, digital communication system becomes high speed, as communication demand dose not only increases sharply, but an image, voice various kinds data also comes multimedia. In transmitting data at a high speed, the main problem is fading by multipath. A linear or nonlinear distortion arise In multipath channel fading from ISI(Intersymbol Interference). For restoring this distorted signal, A lot of equalizer and adaptive algorithm is introduced. This paper compares and analysises, for improving communication quality in channel which is long delay spread, performance of decision feedback equalizer by RLS algorithm, a channel estimation by RLS-MLSE and viterbi equalizer Particularly, there Is exactly channel estimation of impluse response and excellent property of equalization about channel, which delay spread is long impluse response comparatively and is property of non-minimun phase.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.109-112
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• 2001

본 논문은 고속 전력선 통신을 위한 기댐으로 주파수 범위 0∼30MHz에서 BER 개선을 목적으로 DMT 방식을 실험하였다. 송신단에서 길쌈 부호화 방법을 사용했고, 수신단에서는 비터비 알고리즘을 이용해서 복호화 하였으며, 프레임 동기를 위해서 cyclic prefix를 사용하였다. 전력선 채널 특성을 고려하여 거리에 따른 채널 모의실험을 통해서, 코헤어런트 신호를 분석한 결과에 의해 BER을 우수하게 전송시키는 변조 방식을 분석함으로써 전력선상에서 DMT 특성을 이론적으로 분석하여 정보 전달 범위의 효과를 높일 수 있는 방안을 제시하였다.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.05c
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• pp.229-233
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• 2002

비트율 제어 기법은 일정한 양의 비트만을 사용하여 최상의 화질을 얻기 위한 것이다. 기 중에서 최적의 비트율 제어기법(Optimal Rate Control)은 실시간 전송이 필요 없는 응용 분야에서 사용하거나 또는 모델 기반 비트율 제어기법의 성능을 평가하기 위하여 사용되었다. 하지만 기존의 방법들을 저전송율 비디오 부호기에 적용하였을 때에는, 양자화 매개변수간의 의존관계 때문에 최적의 해를 구하지 못하는 문제점이 생겼다. 따라서, 본 논문에서는 라그랑제 비용함수를 사용한 비터비 알고리즘을 이용하여 저 전송율 비디오 부호기에 적용할 수 있는 최적의 비트율 제어기법을 제안할 것이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.9C
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• pp.871-876
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• 2005

In this paper, we propose an improved partial response maximum likelihood (PRML) detection scheme that has an adaptive equalizer and can be applied in the asymmetric optical recording system with high-density. We confirmed that the proposed PRML detector improves detection performance. In addition, we implemented the detector by Verilog HDL. The adaptive equalizer is composed of tap coefficient updating unit using LMS algorithn and FIR filter. FIR filter is implemented by the transposed direct form architecture for high speed operation. Viterbi detector is implemented by the register exchange method.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2565-2567
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• 2004

본 논문에서는 빠르게 변화하는 이동 무선 채널 환경에서 심각한 성능 저하를 일으키는 인접 심볼 간섭(Inter-symbol interference: ISI)에 대처하기 위해 MLSE(Maximum Likelihood Sequence Estimztion) 등화기의 성능을 향상시키는 방법을 제안하였다. 기존의 MLSE 등화기는 비터비 알고리즘으로 어느 정도 계산량을 감소시켰지만, 정확한 채널 임펄스 응답을 필요로 하기 때문에, 시변 채널에서의 복잡한 채널 추정이 그 문제점으로 남아 있다. 이러한 문제점을 해결하기 위해서, 간단하고 향상된 칼만 필터 기반의 채널 추정기를 새롭게 제안하여 MLSE의 복잡성을 줄였다. 또한, 복잡한 채널 추정을 대신하여 페이딩 채널을 거쳐 수신된 데이터를 클러스터로 매핑하여 클러스터 중심 추정을 이용한 1-D CBSE(1-Dimensional Clustering-based Sequence Equalizer) 알고리즘에, 최소 길이를 지닌 훈련 시퀀스를 제안하여 개선된 1-D CBSE을 이용한 MLSE 등화 성능을 보여주었다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• The Journal of Korean Institute of Information Technology
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• v.17 no.3
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• pp.31-41
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• 2019

In this paper, we design and implement the simulator for the transmitter and receiver of 4D-8PSK TCM with 2.0, 2.25, 2.5, and 2.75 bits/symbol-channel transmission efficiency recommended by the CCSDS for satellite communications, and then analyze the BER performance of 4D-8PSK TCM system in AWGN channel. The transmitter of 4D-8PSK TCM is designed in accordance with the recommendation in the CCSDS standard. Meanwhile, for the receiver design of 4D-8PSK TCM, we design the differential decoder generalizing the differential encoder/decoder scheme. The trellis decoding algorithm is designed by applying the auxiliary trellis information and the Viterbi algorithm, and an 8-dimensional constellation mapper equation given in the CCSDS standard is deconstructed to design constellation mapper. Especially, we present the optimized receiver for 4D-8PSK TCM system by investigating the BER performances for the traceback lengths in the Viterbi decoder through computer simulations..

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.07a
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• pp.596-600
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• 2020

본 논문에서는 Xilinx 사(社)의 Spartan-6 FPGA 와 Analog Devices 社의 Transceiver 칩인 AD9361 을 이용한 소프트웨어 정의 라디오 장비인 Universal Software Radio Peripheral(USRP) B210 를 이용하여 디지털 방송 표준인 ATSC 의 실시간 영상 송수신 시스템을 신호 처리 소프트웨어인 그누 라디오로 구현하였다. ATSC 에서 사용하는 MPEG 트랜스포트 스트림 영상 신호가 송신부에서 소프트웨어로 디지털 신호 처리되고 Digital-to-Analog Conversion(DAC) 과정을 거쳐 영상 신호가 송출된다. 본 논문은 디지털 방송 수신부에서 핵심 기능을 하는 등화기 알고리즘을 소프트웨어를 통해 구현하여 신호의 왜곡을 보상하는 방법을 제안한다. 수신부에서는 신호를 수신하여 튜너, 매치 필터, 위상 고정루프, 등화기, 비터비 복호 알고리즘 등의 과정을 거쳐 수신한 후 영상을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.39-48
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• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.