• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.42-48
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• 1999

Consider the situation that informations necessary to solve a certain problem are distributed among processors on a network. It is called a distributed algorithm that in this situation each processor exchanges the message with adjacent processors to solve the problems. This paper proposes a distributed algorithm to solve the problem that constructs the weighted shortest path tree in an asynchronous network system. In general, a distributed algorithm is estimated by the number of messages(message complexity of the distributed algorithm proposed in this paper are O(n53) and O(nln) respectively. where n is the number of processors on the network.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.394-400
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• 2000

The main goal of synchronization is to guarantee exclusive access to shared data and critical sections, and then it makes parallel programs work correctly and reliably. Exclusive access restricts parallelism of parallel programs, therefor efficient synchronization is essential to achieve high performance in shared-memory parallel programs. Many techniques are devised for efficient synchronization, which utilize features of systems and applications. This paper shows the simulation results that existing synchronization methods have inefficiency under CC-NUMA(Cache Coherent Non-Uniform Memory Access) system, and then compares the performance of Freeze&Melt synchronization that can remove the inefficiency. The simulation results present that Test-and-Test&Set synchronization has inefficiency caused by broadcast operation and the pre-defined order of Queue-On-Lock-Bit (QOLB) synchronization to execute a critical section causes inefficiency. Freeze&Melt synchronization, which removes these inefficiencies, has performance gain by decreasing the waiting time to execute a critical section and the execution time of a critical section, and by reducing the traffic between clusters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.105-113
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• 2004

This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

• The Transactions of the Korea Information Processing Society
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• v.6 no.2
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• pp.299-306
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• 1999

Considers the problem to update the spanning tree and strongly-connected components in response to topology change of the network. This paper proposes a distributed algorithm that solves such a problem after several processors and links are added and deleted. Its message complexity and its ideal-time complexity are O(n'log n'+ (n'+s+t)) and O(n'logn') respectively where n'is the number of processors in the network after the topology change, s is the number of added links, and t is the total number of links in the strongly connected component (of the network before the topology change) including the deleted links.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.577-581
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• 2000

폭우선생성트리 등의 문제를 해결하는데 필요한 정보가 네트워크상의 프로세서에 분산되어 있는 상황에서, 그들 정보를 교환하면서 그 문제를 해결하는 알고리즘을 분산알고리즘(Distributed Algorithm)이라고 한다. 폭우선생성트리가 이미 구성되어 있는 비동기식 네트워크상에서 네트워크 형상이 변할 경우, 이로인해 구성되어 있던 폭우선생성트리를 갱신해야 하는 경우가 발생한다. 본 논문에서는 이러한 경우 폭우선생성트리를 효율적으로 갱신하는 메시지 복잡도와 이상시간복잡도 모두 O($p{\surd}q$ + q + a + n')인 분산알고리즘을 제안한다. 여기서, a는 추가 링크의 수, n'는 네트워크의 토폴로지가 변한후의 네트워크상에 존재하는 노드수를 각각 나타낸다. 그리고, p는 삭제 또는 추가 링크를 가진 이중연결성분에 속하는 전체 노드 수를 나타내며, q는 삭제 또는 추가 링크를 가진 이중연결성분에 속하는 전체 링크수를 나타낸다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.826-834
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• 2002

Asynchronous third generation mobile communication system is able to service Packet Switching through adding GPRS Network to the second generation system GSM. Therefore, it is necessary to study packet traffic service of GGSN node which is due to perform gateway role that GPRS Network is enable to inter-connect with Internet in order to optimize the capability and performance of GGSN. In this paper, the Internet packet traffic model that it is arrived to GGSN node from the Internet is studied and In order to process the Inter traffic efficiently, performance analysis model in GGSN is proposed to optimize packet processing capability of each processor. In order to guarantee QoS requirement of the real time traffic Speech and Video, several scheduling algorithm is applied to performance model and each mechanism is compared with several performance parameters.