• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06d
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• pp.23-26
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• 2008

본 논문은 Web 환경에서의 사용자의 권한을 검증하고 권한에 대한 이중적인 접근제어 서비스를 제공하는 역할기반의 WAC 시스템의 블럭 설계서를 제안한다. WAC 시스템은 User Interface Block, Access Control Block, Cipher module Block, DataBase로 구성 되며, WAC 시스템의 기능분류모델을 이용한 Block의 세부사항과 WAC 시스템 기본 Bock(Access Control Bock)의 기본 기능 설계 및 사용자 접근제어 기능 설계, DES 기반의 암호 Bock 기능 설계, 인터페이스 설계 대한 WAC 시스템의 전체적인 Block 설계 에 대하여 기술한다.

• Review of KIISC
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• v.3 no.4
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• pp.69-88
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• 1993

이 시리즈를 시작하면서 제3권 제2호(1993.6)에 sc27국제표준화 현황을 정리해 보고했었다. 필자와 산업연구원의 이경석 박사가 1993년 10월 파리에서 열린 SC27 국제표준 총회에 다녀와 새로 정리된 최신의 표준화현황은 11월 20일 개최되는 1993년도 한국통신정보보호학회 학술대회에서 특별보고회로 발표되며그 내용은 논문집에 포함되어 있으니 참고 바란다. 이번 호에는n비트의 입출력을 갖는 블럭암호화 알고리즘의 사용방법에 관해 1991년에 국제표준이 된 문서 IS 10116를 소개한다. 이보다 앞서 1987년 IS 8372로 거의 같은 내용의 국제표준이 n=64의 경우에 한정되어 만들어져 사용되어왔다. 1992년 정보보안 국제총회에서 IS 10116이 IS8372의 내용을 포함하며 IS 10116가 IS 8372보다 더 잘 서술되어 있으므로 IS 3872를 국제표준으로 놓아두자는 결론을 냈었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• The KIPS Transactions:PartC
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• v.18C no.1
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• pp.7-14
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• 2011

Power analysis attack on low-power consumed security devices such as smart cards is very powerful, but it is required that the correlation between the measured power signal and the mid-term estimated signal should be consistent in a time instant while running encryption algorithm. The power signals measured from the security device applying the random clock do not match the timing point of analysis, therefore random clock is used as counter measures against power analysis attacks. This paper propose a new constant pitch based time alignment for power analysis with random clock power trace. The proposed method neutralize the effects of random clock used to counter measure by aligning the irregular power signals with the time location and size using the constant pitch. Finally, we apply the proposed one to AES algorithm within randomly clocked environments to evaluate our method.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.83-94
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• 2006

This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.