• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.4
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• pp.345-350
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• 2014

DC electrolytic capacitor is widely used in the power converter including PWM inverter, switching power supply and PFC Boost converter system because of its large capacitance, small size and low cost. In this paper, basic characteristics of DC electrolytic capacitor vs. frequency is presented and the real-time estimation scheme of ESR and capacitance based on the bandpass filtering is adopted to the single phase boost converter of uninterruptible power supply to diagnose its split dc-link capacitors. The feasibility of this real-time failure prediction monitoring system is verified by the computer simulation of the 5[kW] singe phase PFC half-bridge boost converter.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.237-239
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• 2003

이 논문은 이중 출력과 단일 역률 적용에 대한 하나의 전력단 회로를 사용한 새로운 정류기를 나타낸다. 제안된 정류기는 부스트와 플라이백 컨버터가 결합된 하나의 전력단 회로를 갖는 구조를 가지고 있고, PFC(power factor correction) 와 일정 출력 전압 제어를 동시에 수행한다. 따라서, 제안된 정류기는 전형적인 AC/DC 정류기들(멀티 권선을 갖는 플라이 백 정류기, 투 스테이지 방식을 사용한 부스트와 플라이백 컨버터가 결합된 정류기 등등)보다 낮은 비용과 작은 사이즈의 장점을 갖는다. 제안된 정류기 회로의 동자 원리는 본 논문에서 상세하게 기술 되어진다. 그리고 시뮬레이션을 통하여 제안된 정류기의 타당성을 증명하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.6
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• pp.496-503
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• 2017

This study proposes a high-performance current control algorithm for a diode-bridge-type single-phase boost power factor correction (PFC) converter. The conventional asynchronous single-phase current controllers that directly control AC-type current tend to be accompanied by steady-state errors due to their poor dynamic characteristics for the transient-state, which can be attributed to bandwidth limitations and phase delays. In the proposed algorithm, an ideal current control with minimal phase delays and steady-state errors can be achieved by using a virtual DQ synchronous reference frame and by controlling the synchronous reference frame excluding the frequency component in the single-phase system. The performance of the conventional asynchronous single-phase current controller is compared with that of the proposed algorithm through simulation and experiments, and the results have confirmed the superiority of the latter.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.6
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• pp.527-534
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• 2017

This paper proposes a new DC link voltage controller for a single-phase power factor correction (PFC) boost converter. The load current of the PFC boost converter affects the capacitor current, whereas the load current changes the output voltage. However, previous works that compensate output current have failed to consider the relationship between load current and duty. Thus, they also fail to maintain a constant output voltage if the load fluctuates under the conditions of a non-rated input voltage. By considering the duty in the load current compensation, the proposed method improves the load transient response regardless of the input voltage. To demonstrate its effectiveness, the proposed method is compared with other control methods by conducting PSM simulations and experiments under a rapidly changing load.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.6
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• pp.515-522
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both v voltage-fed and current-f,어 ek'Ctronic ballast. The proposed PFC circuits use valley-fil[(VF) type DClink s stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations d during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant c capaCltor In current-fed type, the charge pump capacitors are connc'Ctc'Cl with the additional second따y-side of t the power transformer. The measured PF is higher than 0.99 and THD is about 10% for all proposed PFC c circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for i implementing cost longrightarroweffective electronic ballast.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.463-464
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• 2013

본 논문은 전기자동차용 탑재형 배터리 충전기의 효율 개선점 도출을 위해 요구되는 손실 분석 과정을 다룬다. 평균전류모드 부스트 PFC 컨버터와 직렬공진형 DC-DC 컨버터로 구성된 3.3kW급 탑재형 배터리 충전기의 각 부 손실들을 이론적으로 분석하고, 이를 PSIM Simulator의 Thermal Module을 이용한 손실 측정 결과와 비교하여 타당성을 검증한다.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2625-2627
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• 2005

본 논문에서는 TMS320F2812 DSP를 사용하여 PFC를 위한 디지털 제어기를 설계하였다. 디지털제어기를 사용함으로써 윈도우 기반의 PC와 통신을 통해 제어기의 각종 파라미터를 모니터할 수 있고 원격제어가 가능하도록 설계하였다. 설계된 디지털 제어기는 DC 200V출력의 300W급 부스트 컨버터에 적용하였으며, 디지털 제어기를 통하여 입력전류가 입력전압의 위상을 추종제어 됨을 실험을 통하여 확인하였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.843-850
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• 2016

In this paper, we propose a digital controller design process for the interleaved type of a boost PFC (Power Factor Correction) converter which can disperse the heat of the switching devices due to the interleaved topology. We establish a mathematical model of a boost PFC converter and propose a controller design method based on the root locus. The performance of the designed controller is verified by simulations. The measurement of the input voltage, inductor currents, and the converter output link voltage are needed for the control of the converter system which consists of a power unit and a control unit where a high-performance 32-bit microcontroller is used. The adjustment of A/D conversion timing is also needed to avoid high frequency noise generated when the switches on/off. It is illustrated by the real experiments that the designed control system with the properly adjusted ADC timing satisfies the given performance specifications of the interleaved boost PFC converter in the on-board slow battery charger.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.214-222
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• 2015

The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.111-112
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• 2011

대용량 역률 보상 정류기의 스위칭 손실 최소화하기 위해서 인덕터 커플링 방식의 새로운 무손실 스너버 회로를 적용한 역률 보상 정류기 회로를 제안한다. 대용량 역률 보상 정류기 구현에 적합한 CCM 부스트 컨버터의 다이오드 역회복 특성에 따른 문제점을 극복하기 위해서 커플 인덕터를 이용해서 다이오드 턴-오프시 전류의 기울기를 감소시켜 역회복 전류를 줄여 줌으로써 주 스위치의 턴-온 손실을 줄였다. 또한 스위치턴-오프시 발생하는 손실을 최소화하기 위해서 다이오드와 콘덴서를 이용한 무손실 스너버 회로를 설계하였다. 단상 3.3kW 역률 보상회로의 시제품을 제작하여 제안하는 무손실 스너버 회로를 가진 역률보상 정류기의 성능을 검증하였다.