• The KIPS Transactions:PartA
• /
• v.11A no.5
• /
• pp.333-340
• /
• 2004

In order that routers forward a packet to its destination, they perform IP address lookup which determines the next hop according to the packet's destination address. In designing high speed routers, IP address lookup is an important issue. In order to design high speed routers, this paper proposes a parallel IP lookup scheme which consists of several IP lookup engines without any modification of already fabricated indirect IP lookup chipsets. Also, we propose a simple rule for partitioning IP prefix entries In an overall forwarding table among several IP lookup engines. And we evaluate the performance of the proposed scheme in terms of the memory size required for storing lookup information and the number of memory accesses on constructing the forwarding table. With additional hardware logics, the proposed scheme can reduce about 30% of the required memory size and 80% of the memory access counts.

• The Journal of the Korea Contents Association
• /
• v.13 no.2
• /
• pp.44-51
• /
• 2013

Routers should perform fast IP address lookup for Internet to provide high-speed service. In this paper, we present a hybrid parallel IP address lookup structure composed of four-stage pipeline. It achieves parallelism at low cost by using multiple SRAMs in stage 2 and partitioned TCAMs in stage 3, and improves the performance through pipelining. The smart distributor in stage 1 does not transfer any IP address identical to previous one toward the next stage, but only uses the result of the previous lookup. So it improves throughput of lookup by caching effects, and decreases the access conflict to TCAM bank in stage 3 as well. In the last stage, the reorder buffer rearranges the completed IP addresses according to the input order. We evaluate the performance of our parallel pipelined IP lookup structure comparing with previous hybrid structure, using the real routing table and traffic distributions generated by Zipf's law.

• Journal of KIISE:Databases
• /
• v.36 no.2
• /
• pp.84-98
• /
• 2009

Various algorithms and architectures for IP address lookup have been studied to improve forwarding performance in the Internet routers. Previous IP address lookup architecture using Bloom filter requires a separate Bloom filter as well as a separate hash table in each prefix length, and hence it is not efficient in implementation complexity. To reduce the number of hash tables, it applies controlled prefix expansion, but prefix duplication is inevitable in the controlled prefix expansion. Previous parallel multiple-hashing architecture shows very good search performance since it performs parallel search on tables constructed in each prefix length. However, it also has high implementation complexity because of the parallel search structure. In this paper, we propose a new IP address lookup architecture using all-length Bloom filter and all-length multiple hash table, in which various length prefixes are accomodated in a single Bloom filter and a single multiple hash table. Hence the proposed architecture is very good in terms of implementation complexity as well as search performance. Simulation results using actual backbone routing tables which have $15000{\sim}220000$ prefixes show that the proposed architecture requires 1.04-1.17 memory accesses in average for an IP address lookup.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2002.04b
• /
• pp.1297-1300
• /
• 2002

포워딩 엔진은 외부 인터페이스를 통해서 들어오는 패킷에 대해서 IP 주소를 기반으로 목적지로 향하는 다음 홉을 결정한다. 이러한 고속의 패킷 처리를 위한 포워딩 엔진을 설계함에 있어서 IP 주소 탐색은 중요한 요인이다. 본 논문에서는 검색경로 압축 트라이에 기반한 IP 주소 탐색 알고리즘을 병렬화 하는 기법을 제시한다. 제시된 병렬화를 통해서 IP 주소 탐색의 메모리 접근 횟수글 줄일 수 있으며, 고성능의 패킷 포워딩 엔진에 적용할 수 있다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2012.06d
• /
• pp.436-438
• /
• 2012

미래인터넷에 대한 연구가 시작되면서 새로운 네트워크 구조 및 프로토콜에 대한 실험을 용이하게 할 수 있는 소프트웨어 라우터에 대한 관심이 높아지고 있다. 고성능 소프트웨어 라우터를 구현하는 데에 있어서 해결하여야 하는 한가지 문제는 고속의 IP 주소 검색 기능의 구현이다. 최근에 고성능 IP 주소 검색 기능을 GPU의 병렬성을 이용하여 해결하려는 시도가 행해지고 있다. 본 논문에서는 GPU에 적합한 구조를 지닌 고성능의 IP 주소 검색 방법을 제안한다. GFLE라고 명명한 이 방법은 해시 테이블 기반 하에서 GPU에서 캐시 히트를 높일 수 있는 구조를 추가한 것이다. 제안한 방법은 실제 백본 라우터의 라우팅 테이블을 사용한 실험을 통하여 약 180 Mpps의 IP 주소 검색 성능을 나타내며, 기존에 발표된 방법에 비하여 프리픽스 갱신이 용이하다는 장점을 지니고 있다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.3B
• /
• pp.65-71
• /
• 2005

The primary function of the Internet routers is to forward incoming packets toward their final destinations. IP address lookup is one of the most important functions in evaluating router performance since IP address lookup should be performed in wire-speed for the hundred-millions of incoming packets per second. With CIDR, the IP prefixes of routing table have arbitrary lengths, and hence address lookup by exact match is no longer valid. As a result, when packets arrive, routers compare the destination IP addresses of input packets with all prefixes in its routing table and determine the most specific entry among matching entries, and this is called the longest prefix matching. In this paper, based on parallel multiple hashing and prefix grouping, we have proposed a hardware architecture which performs an address lookup with a single memory access.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.2B
• /
• pp.158-166
• /
• 2004

Address lookup is one of the most essential functions of the Internet routers and a very important feature in evaluating router performance. Due to the facts that the Internet traffic keeps growing and the number of routing table entries is continuously growing, efficient address-lookup mechanism is indispensable. In recent years, various fast address-lookup schemes have been proposed, but most of those schemes are not practical in terms of the memory size required for routing table and the complexity required in table update In this paper, we have proposed a parallel IP address lookup architecture based on multiple hashing. The proposed scheme has advantages in required memory size, the number of memory accesses, and table update. We have evaluated the performance of the proposed scheme through simulation using data from MAE-WEST router. The simulation result shows that the proposed scheme requires a single memory access for the address lookup of each route when 203kbytes of memory and a few-hundred-entry TCAM are used.

• Journal of the Korea Society of Computer and Information
• /
• v.15 no.12
• /
• pp.93-100
• /
• 2010

In this paper, we propose a technique which makes it faster to delete prefixes in an IP address lookup architecture based on parallel TCAMs. In previous deletion schemes, more than one memory movement is needed for the prefix ordering and keeping the available memory space consecutive. For deletion, our scheme stores the address of the deleted prefix in a stack implemented by SRAM instead of actual movement in TCAM. Since SRAM has very short latency compared to TCAM, the proposed scheme can accomplish fast updating. From the experiment with the real forwarding table and update trace, we evaluate the performance of our scheme in terms of the memory access time for the prefix insertion and deletion. The experiment result also shows good performance with considerably small size of stack.