• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.41 no.11
• /
• pp.1-7
• /
• 2004

We propose multistage parallel nulling (MPN) partial parallel interference cancellation (PPIC) receiver for downlink multiple-input multiple-output (MIMO) multicarrier (MC)-code division multiple access (CDMA) systems. Though the V-BLAST is a popular MIMO receiver, it shows error floor for multiuser downlink MIMO MC-CDMA systems. The proposed MPN-PPIC receiver does not produce error floor for multiuser case, and achieves substantial performance gains with multistage processing. For single user case, the proposed method also surpasses the V-BLAST receiver with multistage processing for MIMO MC-CDMA systems with chip level interleaving. The system performance of the proposed MPN-PPIC receiver is evaluated through computer simulations.

• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.12
• /
• pp.655-664
• /
• 2002

In many data-parallel applications massive parallelism can be easily extracted through data distribution. But it often causes very long communication latency. This paper shows that task parallelism, which is extracted from data-parallel programs, can be exploited to hide such communication latency Unlike the most previous researches over exploitation of task parallelism which has not been considered together with data parallelism, this paper describes exploitation of task parallelism in the context of data parallelism. PCFG(Parallel Control Flow Graph) is proposed to represent a multithreaded program consisting of a few task threads each of which can include a few data-parallel loops. It is also described how a PCFG is constructed from a source data-parallel program through HDG(Hierarchical Dependence Graph) and how the multithreaded program can be constructed from the PCFG.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.6
• /
• pp.80-87
• /
• 2016

We propose a parallel mesh smoothing algorithm using graph coloring and OpenMP library for shared memory many core computer architectures. The proposed algorithm partitions a mesh into independent sets and performs a parallel mesh smoothing using OpenMP library. We study the effect of using various graph coloring and color reordering algorithms on the efficiency of performing the proposed parallel mesh smoothing algorithm. We also investigate the influence of using various OpenMP loop scheduling methods on the parallel mesh smoothing efficiency.

• Journal of KIISE:Computer Systems and Theory
• /
• v.31 no.8
• /
• pp.421-431
• /
• 2004

This paper presents adaptive execution techniques that determine whether parallelized loops are executed in parallel or sequentially in order to maximize performance. The adaptation and performance estimation algorithms are implemented in a compiler preprocessor. The preprocessor inserts code that automatically determines at compile-time or at run-time the way the parallelized loops are executed. Using a set of standard numerical applications written in Fortran77 and running them with our techniques on a distributed shared memory multiprocessor machine (SGI Origin2000), we obtain the performance of our techniques, on average, 26%, 20%, 16%, and 10% faster than the original parallel program on 32, 16, 8, and 4 processors, respectively. One of the applications runs even more than twice faster than its original parallel version on 32 processors.

• Proceedings of the KIPE Conference
• /
• 2015.07a
• /
• pp.163-164
• /
• 2015

본 논문에서는 고승압비를 갖는 단일스위치 ZCS 병렬 공진 컨버터를 제안한다. 제안하는 컨버터는 단일스위치를 사용하여 구조가 간단하며 병렬 공진회로를 이용하여 고승압이 가능하다. 또한, 별도의 클램프 회로 없이 전 부하영역에서 스위치의 ZCS 턴온 및 턴오프와 다이오드의 ZCS 턴오프를 성취한다. 제안하는 컨버터는 250W 시작품을 제작하여 타당성을 검증하였다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.31 no.7
• /
• pp.379-386
• /
• 2004

We designed a portable parallel library HPCL(High Performance Computing Library) with following objectives: (1) to provide a close relationship between the parallel code and the original sequential code that will help future versions of the sequential code and (2) to enhance performance of the parallel code. The library is an interface written in C and Fortran programming languages between MPI(Message Passing Interface) and parallel programs in Fortran. Performance results were determined on clusters of PC's and IBM SP4.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.6
• /
• pp.1056-1063
• /
• 1994

In this paper a content addressable memory (CAM) is designed by adopting best-match method. It has a single processing element(PE) architecture with high computational efficiency and throughput. It is composed of three main functional blocks(input MUX, best-match CAM, control part). It support fully parallel processing. Logic simulation is completed by using QUICKSIM, Circuit simulation is performanced by using HSPICE. Its layout is based on the ETRI 3 m n-well process design rules. Its maximum operating frequency is 20 MHz.

• Journal of KIISE:Computer Systems and Theory
• /
• v.26 no.1
• /
• pp.98-106
• /
• 1999

본 논문에서는 대용량 입출력을 수행하는 태스크의 QoS를 제어하기 위한 방법으로사용자가 시스템에 입출력 요구시 요구 대역폭을 제시하고, 파일시스템에서 디스크개소와 입출력 이벤트를 고려하여 입출력의 병렬성을 제어함으로써 QoS를 제어하는 방법을 제안하였다. 그리고, 시스템에서 각 태스크가 주어진 병렬성을 가지고 입출력을 진행하고 있을 때, 요구 대역폭을 가지고 입출력을 요구하는 태스크의 대역폭을 만족시키기 위한 병렬성을 계산하는 분석 모델을 유도하였다. 그리고, 디스크 입출력의 병렬성을 이용하여 대용량 입출력의 QoS를 효율적으로 제어할 수 있음을 분석 모델의 결과를 통해 검증하였다.

• NEWSLETTER 전기공업
• /
• no.99-1 s.218
• /
• pp.30-37
• /
• 1999

• Proceedings of the Optical Society of Korea Conference
• /
• 1999.08a
• /
• pp.98-99
• /
• 1999