• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.83-86
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• 2000

DS/CDMA 이동통신 환경에서 채널의 용량을 제한하는 가장 큰 요인은 다중 사용자 간섭 신호의 영향이다. 본 논문에서는 어레이 안테나와 적응 혼합 다중 사용자 검파기 구조 (MUD: Multi-User Detection)를 이용하여 이러한 문제를 제거한다. 어레이 안테나의 각각의 빔 형성기는 MUD에서 궤환되는 기준 신호를 이용하여 원하는 사용자의 방향으로 빔을 형성하고 간섭 신호 방향으로는 널을 형성하여 제거하게 된다. 수신 신호의 전력이 제어되지 못하여 원근 문제(near-far problem)가 발생할 경우, 제안한 MUD는 적응적으로 지배적인 상관 값에 대해서는 직렬형, 비슷한 크기의 신호들은 병렬형 간섭 제거기를 통하여 제거함으로써 기존의 고정형 간섭 제거기보다 우수한 성능을 나타내었다.

• The Journal of the Acoustical Society of Korea
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• v.12 no.1E
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• pp.39-47
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• 1993

2-Dimension IIR 디지털 필터를 시스토릭 어레이 구조로 실현하는 방법을 보였다. 시스토릭 어레이는 1-D IIR 디지털 필터로 부분 실현한 후 종속연결하여 구현하였다. 부분 실현한 시스토릭 어레이의 종속 연결은 신호 지연에 사용되는 요소를 감소 시킨다. 여기서 1-D 시스토릭 어레이는 local communication 접근에 의해 DG를 설계한후 SFG로의 사상을 통해 유도하였다. 유도된 구조는 매우 간단하며, 입력 샘플이 공급되어지면 매 샘플링 기간마다 새로운 출력을 얻는 매우 높은 데이터 처리율을 갖는다. 2-Dimension IIR 디지털 필터를 시스토릭 어레이로 실현함으로써 규칙적이고, modularity, local interconnection, 높은 농기형 다중처리의 특징을 갖기 때문에 VLSI 실현에 매우 적합하다. 또한 PE셀의 승산기 설계에서는 modified Booth's 알고리즘과 Ling's 알고리즘에 기초를 두고 고도의 병렬처리를 행할수 있도록 설계하였다.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.647-650
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• 1988

This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.

• Journal of IKEEE
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• v.28 no.2
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• pp.234-238
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• 2024

This paper presents a study on the integration of 3D-stacked dual-tip RRAM with a CNN accelerator architecture, leveraging its low drive current characteristics and scalability in a 3D stacked configuration. The dual-tip structure is utilized in a parallel connection format in a synaptic array to implement multi-level capabilities. It is configured within a Network-on-chip style accelerator along with various hardware blocks such as DAC, ADC, buffers, registers, and shift & add circuits, and simulations were performed for the CNN accelerator. The quantization of synaptic weights and activation functions was assumed to be 16-bit. Simulation results of CNN operations through a parallel pipeline for this accelerator architecture achieved an operational efficiency of approximately 370 GOPs/W, with accuracy degradation due to quantization kept within 3%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1047-1054
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• 2004

In this paper, we present two systolic arrays for computing multiplications in CF(2$\^$m/) generated by an irreducible all one polynomial (AOP). The proposed two systolic mays have parallel-in parallel-out structure. The first systolic multiplier has area complexity of O(㎡) and time complexity of O(1). In other words, the multiplier consists of m(m+1)/2 identical cells and produces multiplication results at a rate of one every 1 clock cycle, after an initial delay of m/2+1 cycles. Compared with the previously proposed related multiplier using AOP, our design has 12 percent reduced hardware complexity and 50 percent reduced computation delay time. The other systolic multiplier, designed for cryptographic applications, has area complexity of O(m) and time complexity of O(m), i.e., it is composed of m+1 identical cells and produces multiplication results at a rate of one every m/2+1 clock cycles. Compared with other linear systolic multipliers, we find that our design has at least 43 percent reduced hardware complexity, 83 percent reduced computation delay time, and has twice higher throughput rate Furthermore, since the proposed two architectures have a high regularity and modularity, they are well suited to VLSI implementations. Therefore, when the proposed architectures are used for GF(2$\^$m/) applications, one can achieve maximum throughput performance with least hardware requirements.

• Journal of the Korean Solar Energy Society
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• v.36 no.4
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• pp.57-65
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• 2016

Domestic photovoltaic system for roof-top is installed towards the south at an angle of 20 to 35 degrees and the shape of PV array is divided into two kinds; a plane shape and a curved shape. This paper aims to understand an actual condition of PV facility and strengths and weaknesses of support structure production and installation and to consider the best PV surface shape by analyzing theoretical logics of these two surface shapes and architectural perspective-based realistic case studies. This study targeted 98 facilities including common houses, public institutions and education institutions. In common houses, all of 59 PV facilities have a plane surface. In public institutions, 7 of 15 PV facilities have a curved array surface and 8 PV facilities have a plane surface. In education institutions, also, 14 of 24 PV facilities have a plane array surface and 10 PV facilities have a curved surface. Most of 98 facilities have a flat roof supporting shape. However, it was found that the curved shape wasn't positive for PV generation due to the change of radial density and it was at least 10 % more expensive to produce its structure. Also, domestic general large single-plate PV facilities have problems of harmony with buildings and wind load. Therefore, it is considered that for fixed-type roof-top PV, a plane PV array shape is good for optimum generation and economic efficiency and a parallel array structure on the roof surface is favorable to wind load and snow load without being a hindrance to the building facade.