• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.129-131
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• 2015

스마트 그리드는 에너지 이용 효율 최적화를 위한 개선방안으로 전기에너지를 발생하는 발전원별 분석하며, 전력 사용 측면에서 전력망을 통해 공급된 전력의 소비패턴으로 분석을 통해 에너지 이용 효율을 최적화할 수 있다. 본 논문에서는 아파치 Storm을 활용하여 실시간 데이터 수집 및 처리 시스템을 설계한다. 설계된 시스템은 에너지 효율성을 위해 이종의 실시간 대용량 스트리밍 센서 데이터를 수집하여 분석을 수행하도록 데이터 필터링과 변환 기법을 제시한다. 이를 위해 실시간 대용량 처리를 위해 필터링 및 변환을 병렬 처리하도록 한다. 필터링과 변환 처리는 독립적인 타스크로 구성하도록 하며, 전체 프로세스는 정의된 파이프-필터 토폴로지를 구성하여 처리한다.

• The KIPS Transactions:PartD
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• v.14D no.2
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• pp.157-168
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• 2007

For effective analyses in various business applications, OLAP(On-Line Analytical Processing) systems represent the multidimensional data as the horizontal format of tables whose columns are corresponding to values of dimension attributes. Because the traditional RDBMSs have the limitation on the maximum number of attributes in table columns(MS SQLServer and Oracle permit each table to have up to 1,024 columns), horizontal tables cannot be directly stored into relational database systems. In this paper, we propose various efficient optimization strategies in transforming horizontal queries to equivalent vertical queries. To achieve this goral, we first store a horizontal table using an equivalent vertical table, and then develop various query transformation rules for horizontal table queries using the PIVOT operator. In particular, we propose various alternative query transformation rules for the basic relational operators, selection, projection, and join. Here, we note that the transformed queries can be executed in several ways, and their execution times will differ from each other. Thus, we propose various optimization strategies that transform the horizontal queries to the equivalent vertical queries when using the PIVOT operator. Finally, we evaluate these methods through extensive experiments and identify the optimal transformation strategy when using the PIVOT operator.

• Journal of the korean Society of Automotive Engineers
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• v.11 no.2
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• pp.24-33
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• 1989

본 고에서는 이러한 추세에 따라서, 보다 효율적인 optimization program에 대해서 소개하고자 한다. 사용한 최적화 알고리즘은 ALM(augmented lagrange multiplier) 방법을 적용해서 구속조건이 있는 문제를 구속조건이 없는 문제로 변환한 후, self-scaling BFGS(broydon-flecher-goldfarb-schanno)를 적용한다. BFGS의 각 descent 방향에서의 step 길이는, sequential search로 unimodal point를 구해서, golden section 방법으로 refine을 한후, cubic approximation을 적용해서 구한다.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.109-114
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• 2011

We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.2 s.314
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• pp.93-101
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• 2007

To jointly optimize the spatial registration and the exposure compensation, an iterative registration algorithm, the Lucas-Kanade algorithm, is combined with an exposure compensation algorithm, which is based on the histogram transformation function. Based on a simple regression model, a nonparametric estimator, the empirical conditional mean, and its polynomial fitting are used as histogram transformation functions for the exposure compensation. Since the proposed algorithm is composed of separable optimization phases, the proposed algorithm is more advantageous than the joint approaches of Mann and Candocia in the aspect of implementation flexibility. The proposed algorithm performs a better registration for real images than the case of registration that does not consider the exposure difference.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.122-131
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• 2010

In this paper, we design and implement CTOC, a new bytecode analysis and translation tool. We also propose E-Tree, a new intermediate code, to efficiently deal with intermediate codes translated from bytecodes. E-Tree is expressed in a tree form by combining relevant bytecode instructions in basic blocks of eCFG to overcome the weaknesses of bytecodes such as complexity and analytical difficulty. To demonstrate the usefulness and possible extensibility of CTOC, we show the creation process of eCFG and E-Tree through practical bytecode analysis and translation and shows the optimization process of a bytecode program as an example of possible extensibility.

• Plant Journal
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• v.13 no.3
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• pp.26-29
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• 2017

In this research, the composition of the feed stream is optimized in pressure swing distillation for separating of methanol-acetone. It is well known that the composition of feed stream in pressure swing distillation system has a great influence on the feasibility to separate mixture. The workscope of this study is to show better separation efficiency at specified pressure by controlling the composition of feed stream with recycle of two products. Based on the base case without recycle flow, two processes are designed that methanol and acetone are recycled to feed stream, respectively. Each processes are compared with total annual cost and as a result, the base case without recycle flow are most favorable.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.541-544
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• 2001

The difference of transfer mode between TDMA and ATM causes cell delay variation(CDV) to be generated in the receiving station. I proposed a optimization method of timestamps for discrete-timestamps mechanism to compensate CDV and an application method in multiple timestamps mechanism.

• Journal of the Korea Society of Computer and Information
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• v.12 no.2 s.46
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• pp.1-8
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• 2007

Although the Java bytecode has numerous advantages, there are also shortcomings such as slow execution speed and difficulty in analysis. Therefore, in order for the Java class file to be effectively executed under the execution environment such as the network, it is necessary to convert it into optimized code. We implements CTOC. In order to statically determine the value and type, CTOC uses the SSA Form which separates the variable according to assignment. Also, it uses a Tree Form for statements. But, due to insertion of the $\phi$-function in the process of conversion into the SSA Form, the number of nodes increased. This paper shows the dead code elimination to obtain a more optimized code in SSA Form. We add new live field in each node and achieve dead code elimination in tree structures. We can confirm after dead code elimination though test results that nodes decreases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.6
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• pp.813-818
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• 2021

This paper proposes an optimized hardware implementation method for existing CIE1931 color gamut control algorithm. Among the post-processing methods of dehazing algorithms, existing algorithm with relatively low computations have the disadvantage of consuming many hardware resources by calculating large bits using Split multiplier in the computation process. The proposed algorithm achieves computational reduction and hardware miniaturization by reducing the predefined two matrix multiplication operations of the existing algorithm to one. And by optimizing the Split multiplier computation, it is implemented more efficient hardware to mount. The hardware was designed in the Verilog HDL language, and the results of logical synthesis using the Xilinx Vivado program were compared to verify real-time processing performance in 4K environments. Furthermore, this paper verifies the performance of the proposed hardware with mounting results on two FPGAs.