• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.13-17
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• 2006

Dense and periodic arrays of holes and tungsten none dots were fabricated on silicon oxide and silicon. The holes were approximately 25 nm wide, 40 nm deep, and 60 nm apart. To obtain nano-size patterns, self-assembling resists were used to produce layer of hexagonally ordered parallel cylinders of polymethylmethacrylate(PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS mask for pattern transfer. The silicon oxide was removed by fluorine-based reactive ion etching(RIE). Selectively deposited tungsten nano dots were formed inside nano-sized trench by using a low pressure chemical vapor deposition(LPCVD) method. Tungsten nano dot and trenched silicon sizes were 26 nm and 30 nm, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.2 s.43
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• pp.17-21
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• 2007

Dense and periodic arrays of holes and Si nano dots were fabricated on silicon substrate. The nanopatterned holes were approximately $15{\sim}40nm$ wide, 40 nm deep and $40{\sim}80\;nm$ apart. To obtain nano-size patterns, self?assembling diblock copolymer were used to produce layer of hexagonaly ordered parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS. $100\;{\AA}-thick$ Au thin film was deposited by using e-beam evaporator. PS template was removed by lift-off process. Arrays of Au nano dots were transferred by using Fluorine-based reactive ion etching(RE). Au nano dots were removed by sulfuric acid. Si nano dots size and height were $30{\sim}70\;nm$ and $10{\sim}20\;nm$ respectively.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.29-32
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• 2009

Dense and periodic arrays of nano-sized holes were patterned in oxide thin film on GaAs substrate. To obtain the nano-size patterns, self-assembling diblock copolymer was used to produce thin film of uniformly distributed parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene (PS) matrix. The PMMA cylinders were removed with UV expose and acetic acid rinse to produce PS nanotemplate. By reactive ion etching, pattern of the PS template was transferred to under laid silicon oxide layer. Transferred patterns were reached to the GaAs substrate by controlling the dry etching time. We confirmed the achievement of etching through the removing oxide layer and observation of GaAs substrate surface. Optimized etching time was 90 to 100 sec. Pore sizes of the nanopattern in the silicon oxide layer were 20~22 nm.