• Journal of the Korea Society of Computer and Information
• /
• v.16 no.2
• /
• pp.1-8
• /
• 2011

NAND type Flash memory has performing much researches for a hard disk substitution due to its low power consumption, cheap prices and a large storage. Especially, the NAND type flash memory is using general buffer systems of a cache memory for improving overall system performance, but this has shown a tendency to emphasize in terms of data. So, our research is to design a high performance instruction NAND type flash memory structure by using a buffer system. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer for branch instruction and a fully associative spatial buffer for spatial locality. The spatial buffer with a large fetching size turns out to be effective serial instructions, and the temporal buffer with a small fetching size can achieve effective branch instructions. According to the simulation results, we can reduce average miss ratios by around 77% and the average memory access time can achieve a similar performance compared with the 2-way, victim and fully associative buffer with two or four sizes.

• Proceedings of the Korean Information Science Society Conference
• /
• 2005.07a
• /
• pp.793-795
• /
• 2005

영속적인 데이터 저장이 가능한 차세대 비휘발성 메모리를 휘발성 메모리와 혼용하여 버퍼캐처로 사용하면, 안정성과 성능향상의 효과를 얻을 수 있다. 본 연구에서는 기존의 연구에서 제시한 캐처관리 정책을 시뮬레이터를 이용하여 실험하고 실험 결과를 분석하여 비휘발성 메모리가 추가된 캐처의 새로운 특성을 밝혀냈다. 비휘발성 메모리가 캐쉬에 포함되면 읽기 쓰기의 요청의 종류, 미스(miss)되었을 경우 캐쉬될 블록의 더티(dirty)여부, 읽기 요청이 적중(hit)되었을 때, 적중된 블록의 메모리 종류에 따라 각각의 요청을 처리하기 위한 디스크 접근횟수가 달라지는 특성을 나타낸다. 이 특성 때문에 비휘발성 메모리가 추가된 버퍼캐처는 적중률(hit rate) 보다는 디스크 접근횟수를 측정하는 것이 정확한 성능측정을 가능하게 한다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.3
• /
• pp.324-336
• /
• 2000

The paper proposes an efficient buffer management scheme to enhance performance of the disk I/O system. Without any user level information, the proposed scheme automatically detects the block reference patterns of applications by associating block attributes with forward distance of a block. Based on the detected patterns, the scheme applies an appropriate replacement policy to each application. We also present a new block allocation scheme to improve the performance of buffer cache when kernel needs to allocate a cache block due to a cache miss. The allocation scheme analyzes the cache hit ratio of each application based on block reference patterns and allocates a cache block to maximize cache hit ratios of system. These all procedures are performed on-line, as well as automatically at system level. We evaluate the scheme by trace-driven simulation. Experimental results show that our scheme leads to significant improvements in hit ratios of cache blocks compared to the traditional schemes and requires low overhead.

• Proceedings of the Korean Information Science Society Conference
• /
• 2000.10a
• /
• pp.36-38
• /
• 2000

데이터베이스 공유 시스템(Database Sharing System: DSS)은 고성능 트랜잭션 처리를 위해 다수 개의 컴퓨터를 연동하는 방식으로, 각 노드들은 디스크 계층에서 데이터베이스를 공유한다. DSS에서 각 노드는 빈번한 디스크 액세스를 피하기 위해 최근에 액세스한 데이터 페이지와 인덱스 페이지들을 자신의 지역 메모리 버퍼에 캐싱한다. 이때 노드가 항상 최신의 페이지를 사용할 수 있기 위해서는 지역 버퍼에 캐싱된 페이지들의 일관성을 지원하여야 한다. 본 논문에서는 데이터 페이지에 비해 빈번히 엑세스되는 인덱스 페이지의 정확성을 보장할 수 있는 캐쉬 일관성 제어 기법을 제안한다.

• The KIPS Transactions:PartA
• /
• v.16A no.2
• /
• pp.69-78
• /
• 2009

One of the most effective way to improve cache performance is to exploit both temporal and spatial locality given by any program executive characteristics. In this paper we present a high performance and low power cache structure with a bank selection mechanism that enhances exploitation of spatial and temporal locality. The proposed cache system consists of two parts, i.e., a main direct-mapped cache with a small block size and a fully associative buffer with a large block size as a multiple of the small block size. Especially, the main direct-mapped cache is constructed as two banks for low power consumption and stores a small block which is selected from fully associative buffer by the proposed bank selection algorithm. By using the bank selection algorithm and three state bits, We selectively extend the lifetime of those small blocks with high temporal locality by storing them in the main direct-mapped caches. This approach effectively reduces conflict misses and cache pollution at the same time. According to the simulation results, the average miss ratio, compared with the Victim and STAS caches with the same size, is improved by about 23% and 32% for Mibench applications respectively. The average memory access time is reduced by about 14% and 18% compared with the he victim and STAS caches respectively. It is also shown that energy consumption of the proposed cache is around 10% lower than other cache systems that we examine.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.12
• /
• pp.3642-3651
• /
• 1999

In this paper, we propose a new caching scheme for continuous media data where the buffer allocation unit is divided into two modes : interval and object. All of objects' access patterns are monitored and based on the results of monitoring, a request for an object is decided to cache its data with either interval mode or object mode. The results of our simulation show that our proposed caching scheme is better than the existing caching algorithms such as interval caching where the access patterns of the objects are changed with time.

• Journal of KIISE:Computer Systems and Theory
• /
• v.28 no.1_2
• /
• pp.33-44
• /
• 2001

최근 버퍼 캐쉬의 성능을 향상시키기 위한 많은 블록 교체 기법들이 제안되었으며 이 중에서 작업 집합 (working set) 변화에 잘 적응하고 구현이 용이한 Least Recently Used (LRU) 블록 교체 기법이 널리 사용되고 있다. 그러나 LRU 블록 교체 기법은 블록들이 규칙적인 참조 패턴을 보이면서 순차 참조되거나 순환 참조될 때 이 규칙성을 적절히 이용하지 못해 성능이 저하되는 문제점을 가진다. 본 논문에서는 다중 응용 트레이스를 이용하여 LRU 블록 교체 기법의 문제점을 관찰하고, 이 문제점을 해결하는 통합된 형태의 효율적인 버퍼 관리 (Unified Buffer Management, 이하 UBM) 기법을 제안한다. UBM 기법은 순차 참조 및 순환 참조를 자동 검출하여 분리된 공간에 저장하고 이들 참조에 적합한 블록 교체 기법으로 이 공간을 관리한다. 또한 순차 참조와 순환 참조를 위한 공간과 나머지 참조를 위한 공간의 비율을 최적으로 할당하기 위해 온라인에서 수집된 정보를 이용하여 계산된 단위 공간 증가당 예상 버퍼 적중 증가율을 이용한다. 다중 응용 트레이스 기반 시뮬레이션 실험에서 UBM 기법의 버퍼 적중률은 LRU 블록 교체 기법에 비해 평균 12%, 최대 28%까지 향상된 결과를 보였다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2002.04a
• /
• pp.166-168
• /
• 2002

본 논문에서는 Mobile IP에서 핸드오프 중에 발생하는 패킷손실을 제거하기 위한 신뢰성 있는 핸드오프 기법을 제안하였다. 기존에 제시된 핸드오프 기법은 핸드오프 중에 발생하는 패킷손실을 줄여주지만 여러가지 문제점을 가지고 있었다. 본 논문에서는 캐쉬 에이전트(Cache Agent)가 대응 노드(Correspondent Node)를 대신하여 바인딩 캐쉬를 관리하며 대응 노드가 이동 노드(Mobile Node)에게 전송한 패킷을 버퍼링함으로써 핸드오프 중에 발생하는 패킷손실을 제거한다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.6B
• /
• pp.867-874
• /
• 2010

Since high packet losses occur in multi-hop transmission of wireless sensor networks, reliable data transmission is required. Especially, in case of event-driven data, a loss recovery mechanism should be provided for lost packets. Because retransmission for lost packets is requested to a node that caches the packets, the caching node should maintains all of data for transmission in its buffer. However, nodes of wireless sensor networks have limited resources. Thus, both a loss recovery mechanism and a buffer management technique are provided for reliable data transmission in wireless sensor networks. In this paper, we propose a buffer management technique at a caching position determined by a loss recovery mechanism. The caching position of data is determined according to desirable reliability for the data. In addition, we validate the performance of the proposed method through computer simulations.

• Journal of Korea Multimedia Society
• /
• v.10 no.9
• /
• pp.1197-1208
• /
• 2007

These days, most of SMART card, JAVA card, picked up the JAVA Card Platform gets the position as a standard. Java Card technology provides implantation, platform portability and high security function to SMART Card. Compared to normal Smart Card, JAVA card has a defect that is a low running speed caused by a distinctive feature of JAVA programming language. Factors that affect JAVA Card execution speed are the method how to save the data and install the applets of JAVA Card installation instrument. In this paper, I will offer the plan to improve JAVA Card program's loading and execution speed. At Java Card program, writing, updating and deleting process for data at EEPROM can be improved of Java Card speed by using high speed RAM. For this, at JAVA Card as a application of RAM, I will present prefetching LRU-ORL Buffer Cache Technique that is suitable for Java Card environment. As a data character, managing all data created from JAVA Curd at Buffer Cache, decrease times of recording at maximum for EEPROM so that JAVA Card program upload and execution speed will be improved.