• Journal of Korea Society of Industrial Information Systems
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• v.10 no.1
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• pp.49-57
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• 2005

ATM Form has defined the guaranteed frame rate (GFR) service to provide minimum cell rate (MCR) guarantees for TCP traffic in ATM networks and allow it to fairly share residual bandwidth. GFR switch implementation consists of the frame-based generic cell rate algorithm (F-GCRA) and a frame forwarding mechanism. The F-GCRA identifies frames that are eligible for an MCR guarantee. The frame forwarding mechanism buffers cells at a frame unit according to information provided by the F-GCRA and forwards the buffered cells to an output port according to its scheduling discipline. A simple GFR mechanism with shared buffer with a global threshold is a feasible implementation mechanism, but has been known that it is insufficient to guarantee the MCR. This paper has estimated performance of GFR service for TCP traffic over ATM switches with the simple FIFO-based mechanism

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.24-32
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• 1998

The bus contention among bus-based shared-memory multiprocessors limits their performance. In addition, under split bus transaction environment, multiprocessors may make some memory requests unnecessary stand by in the memory access buffer, which makes system performance worse. This unnecessary stand-by can be eliminated by maintaining the bitmap table which contains the status bit for each memory block. However, this mechanism requires a great size of SRAM for the status information, which is fully mapped from the whole memory blocks. To solve this problem, we propose a bitmap cache which exploits partial mapping and locality of references. The simulation results show that the proposed system can greatly reduce the capacity of SRAM for the status information with little deteriorating its performance.

• The KIPS Transactions:PartC
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• v.12C no.2 s.98
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• pp.183-190
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• 2005

In this thesis, first, we propose I-frame encryption techniques of video data for video data itself encryption and propose license agent that processing user's certification and decryption in client system automatically when user execute encrypted video data in system server. License agent runs user's certification, encryption and decryption of video data based on PID(Public Key Infrastructure) using shared key-pool when execute of video data. Also, compose duplex buffer control and propose real time decryption method using efficient buffer scheduling to reduce much playing delay times that happen processing decryption when execute of videoa data of high-capacity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1497-1501
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• 2005

Branch instructions which make the sequential instruction flow changed cause pipeline stalls in microprocessor. The pipeline hazard due to branch instructions are the most serious problem that degrades the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the hanch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a ta8 memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single combined tag memory, we can expect the smaller chip size and the faster prediction. This shared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.80-90
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• 1996

The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{\times}8$ 150Mb/s or $16{\times}16$ 150Mb/s, the unit switch of $32{\times}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{\times}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{\times}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.

• Journal of Digital Convergence
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• v.12 no.10
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• pp.317-327
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• 2014

To improve the efficiency of wireless channel, IEEE 802.11ac uses the DL MU-MIMO MAC scheme through which an AP transmits multiple frames to different mobile nodes simultaneously. IEEE 802.11ac DL MU-MIMO MAC needs a new step, called as TXOP sharing, between legacy IEEE 802.11n DL SU-MIMO's two operations, the obtaining an EDCA TXOP and the transmitting multiple frames for EDCA TXOP. In the TXOP sharing operation, both wireless channel destinations and frames transmitted for its TXOP period should are determined. So this paper deals with the TXOP sharing for improving IEEE 802.11ac MAC performance. However, the EDCA priority based method mentioned by IEEE 802.11ac standard document not fair among the buffers and the frames of buffers, and occurs in high_loss rate and high_delay about specific buffers. In this paper, we propose a new scheme of the TXOP sharing with sequencing p-AC, s-AC in similar properties, and all S-AC. This method provides a differentiated service without damage of EDCA characteristics.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.235-237
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• 2003

멀티미디어 데이터 전송이 가능한 초고속 통신망의 발달로 음성을 위주로 서비스하던 과거와는 다른 self-similar 특성을 갖는 데이터 트래픽이 발생된다는 것이 알려지고 있다. 이러한 트래픽은 전통적인 네트워크 해석 방법인 포와송 트래픽 모델과는 상당히 차이가 난다는 것이 여러 트래픽의 측정 결과 나타나고 있다. 본 논문에서는 공유 메모리를 갖는 CS(Complete Sharing), DT(Dynamic Threshold), PO(Push-Out) 그리고, SMXQ(Sharing with Maximum Queue)와 같은 다양한 ATM(Asynchronous Transfer Mode) 스위치의 버퍼 관리 기법을 이용하여 입력포트에 self-similar 성질을 갖는 트래픽이 들어올 때 출력포트에서의 self-similarity와 셀 손실률 그리고, 이용률 등을 분석한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10B
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• pp.854-861
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• 2003

In this paper, we proposed the fuzzy control algorithm for efficient buffer control about traffic that is connected in ATM networks. The proposed Fuzzy control algorithm has total traffic arrival ratio, buffer occupancy ratio and Fuzzy set to search for dynamic service rates in server. That is, is based on Fuzzy logic according to the arrival ratio of total traffic and buffer occupancy ratio that is happened and reasoning. Then, made reasoning result control service rates in server about traffic that is connected with defuzzification value. Performance analysis result: it was confirmed that with the proposed scheme, performance improves at cell loss rate, when compared with the existing PBS scheme.

• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.889-896
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• 2006

ATM Forum has defined a guaranteed frame rate (GFR) service to serve Internet traffic efficiently. The GFR service provides virtual connections (VCs) for minimum cell rate (MCR) guarantees and allows them to fairly share the residual bandwidth. And ATM Forum has recommended a frame-based generic cell rate algorithm (F-GCRA) as a frame classifier, which determines whether an Am cell is eligible to use the guaranteed bandwidth in a frame level. An ATM switch accommodates cells in its buffer or drops them in a frame level according to current buffer occupancy. A FIFO shared buffer has so simple structure as to be feasibly implemented in switches, but has not been able to provide an MCR guarantee for each VC without buffer management based on per-VC accounting. In this paper, we enhance the F-GCRA frame classifier to guarantee an MCR of each VC without buffer management based on per-VC accounting. The enhanced frame classifier considers burstness of TCP traffic caused by congestion control algorithm so as to enable each VC to use its reserved bandwidth sufficiently. In addition, it is able to alleviate the unfairness problem in usage of the residual bandwidth. Simulation results show that the enhanced frame classifier satisfies quality of services (QoSs) of the GFR service for the TCP traffic.