• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.28-36
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• 1998

We have proposed a new non-inverting SOI buffer circuit for the high speed operation at low supply voltage. The body biases of main MOS devices in the proposed circuit are controlled dynamically via subsidiary MOS device connected efficiently to the body terminal. We showed current derivability of the body controlled devices obtained by device simulation and compared with that of conventional SOI devices. Delay time characteristics of the buffer circuit were analyzed by SPICE simulation and compared with those of conventional SOI CMOS buffer circuits. Delay time reduction of the SOI buffer over conventional SOI CMOS buffer with same area is about 36 % at $V_{S}$=1.2 V and $C_{L}$=2 pF. pF.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.10
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• pp.24-33
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• 2001

Delay, delay variation and packet loss rate are principal QoS(Quality of Service) elements of packet communication. This paper proposes a new buffer allocation mechanism to improve the packet loss performance in such a situation that multiple logical buffers share a single physical memory buffer. In the proposed buffer allocation mechanism, the movement of dynamic threshold follows a curved track instead of a straight line which is used in the DT(dynamic threshold) mechanism. In order evaluate the effectiveness of the proposed mechanism, it is compared with the existing previously proposed mechanisms in several aspects including NC(no control), ST(Static Threshold) and DT mechanisms.

• The Journal of the Korea Contents Association
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• v.5 no.5
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• pp.248-254
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• 2005

The existing buffer management scheme is caused by with burstness characteristic of the TCP traffic and with only the transmission which is not loss it provides the smallest transmission rate guarantee where the GFR demands and a fair characteristic. In order to provide a high fair characteristic from the dissertation which it sees with the smallest transmission rate guarantee where the GFR demands it proposed the existing buffer algorithm which applies a Fuzzy mechanism in the existing buffer management technique. The proposed algorithm decides a packet disuse used by three parameters which are composed of tagging information, the buffer usage, and the load of VC. Simulation results shows that the fairness and goodput of the proposed algorithm were excellent where the size of MCR will become larger, from the switch the Double-EPD or the DFBA was visible a similar efficiency even from size change of the buffer. The algorithm which is proposed provides a good throughput and a fair characteristic.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1667-1670
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• 2005

본 논문에서는 차세대 통신 플랫폼을 위한 PCI Express의 전송계층과 데이터 연결계층의 모든 기능을 지원하는 PCI Express 컨트롤러를 설계하였다. 설계되어진 컨트롤러는 재전송 매커니즘을 효과적으로 지원하기 위해 제안되어진 송신버퍼 구조를 가지고 있다. 이 버퍼 구조는 전송 버퍼와 재전송 버퍼를 한 개의 버퍼로 통합하여 재전송 버퍼의 공간을 유동적으로 할당할 수 있는 방법이다. 또한 설계되어진 컨트롤러의 송신단 전송계층은 제안되어진 버퍼 구조 효과적으로 지원하도록 설계되어 졌다. 설계 되어진 컨트롤러의 각 블록을 효과적으로 관리하기 위해 80C51 마이크로프로세서를 내장하여 PCI Express 프로토콜을 제공하는 프로그램을 코딩하여 포팅하였다. 또한 설계되어진 컨트롤러의 검증을 위해, Host Bridge, 로컬 마스터 디바이스, 로컬 슬레이브 디바이스를 버스 동작 모델로 구성된 테스트 벤치도 제안하였다. 또한 실제 PCI Express 프로토콜 상에서 발생할 수 있는 모든 경우를 발생 하도록 하기 위해, 각 버스 동작 모델을 위한 어셈블러 명령어들을 정의 하였다.

• Journal of Internet Computing and Services
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• v.5 no.1
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• pp.41-49
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• 2004

Analytical performance evaluation is crucial for justifying the merit of the design of Multistage Interconnection Networks(MINs) in different operational conditions. While several analytical models have been proposed for the performance evaluation of MlNs, they are mainly for uniform traffics. Even the models for nonuniform traffics have various shortcomings. In this paper, an accurate model for the performance evaluation of multi buffered banyan-type MIN's under nonuniform traffic condition is obtained. The accuracy of proposed models are conformed by comparing with the results from simulation.

• Journal of KIISE
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• v.43 no.2
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• pp.177-185
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• 2016

In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.

• Journal of Power System Engineering
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• v.12 no.1
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• pp.20-27
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• 2008

수소 추출과 리포밍 과정, 연료 전지, 저장소로 구성된 수소 연료에 대한 연구는 세계적으로 번영하고 있는 중이다. 그러나 한국의 수소 스테이션에 대한 연구는 아직도 개발이 미미한 수준이다. 그리고 역시 수소 스테이션의 가장 중요한 부분인 수소 압축기에 대한 연구도 미흡하다. 수소압축기에서 가장 중요한 부분 중에 하나는 스너버인데 이것의 기능은 수소가스의 맥동압을 줄이고 불순물을 제거한다. 스너버 내부에는 버퍼라고 불리는 기울어진 판이 설치되어 맥동압을 줄이고 불순물을 제거하는 역할을 담당한다. 스너버 내부의 압력 손실과 맥동압이 최소가 될 때 스너버는 적절한 성능을 가졌다고 평가된다. 그러므로 이 연구의 목적은 수치해석을 통하여 스너버의 최적의 기하학적 크기와 버퍼의 각도에 따른 최적의 스너버를 찾는 것이다. 수치해석의 결과에서 다양한 버퍼각도에 따른 스너버의 독특한 특성을 볼 수 있다. 결과적으로 버퍼의 각도가 $35^{\circ}$일때 최소의 압력손실율이 발생했고, 버퍼의 각도가 $10^{\circ}$일 때 최소의 맥동압이 발생하였다.

• Journal of KIISE:Information Networking
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• v.30 no.4
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• pp.513-519
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• 2003

In order to deliver multicast traffic efficiently, multicast routing and reliable transmission mechanisms are required. The reliable delivery implies that lost packets must be retransmitted, which in turn requires that transmitted packets be stored in a retransmission buffer. Therefore how to manage a retransmission buffer is important and, in this paper, we try to solve the problem of how many packets should be maintained in the buffer. Our proposed scheme, the timer-based buffer management (TBM), maintains only necessary amount of buffer based on the timer value calculated from the NAKs between the replier and receivers on a multicast tree and can adjust to the dynamic network conditions. By performing simulations, we show that TBM manages the buffer efficiently regardless of the error situation, network size, and so on.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.309.1-309.1
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• 2013

현재까지 CIGS 박막 태양전지는 습식공정인 화학적 용액성장법을 사용하여 형성된 CdS버퍼층을 적용할 경우에 가장 높은 효율을 보이고 있다. 그러나, Cd의 독성 문제와 진공 공정과 호환되지 않는 습식공정 때문에 비독성 건식 공정 버퍼층에 대한 연구가 활발히 진행되고 있다. 습식 공정 CdS 버퍼층을 대체하기 위하여 CdS에 비해 밴드갭이 커서 단파장에서 광 손실이 적은 ZnS 버퍼층을 cracker 황화법을 이용하여 제작하여 CIGS 박막 태양전지에 적용하였다. ZnS 버퍼층을 성장시키기 위해 DC 스퍼터를 사용하여 Zn 박막을 증착한 후, cracker를 사용하여 황화반응을 시켰다. cracker의 cracking zone 온도에 따른 S 반응성을 ZnS 박막의 투과도 변화를 통하여 관찰하였다. 성장된 ZnS 박막은 X-ray diffraction와 Rutherford backscattering spectrometry을 이용하여 박막의 결정성과 조성을 분석하였고, SEM 측정을 통하여 박막의 단면 및 표면 형상을 관찰하였다. 그리고 reflection electron energy loss spectroscopy 분석을 통해 밴드갭을 측정하였다. $700^{\circ}C$의 cracking zone 온도, 3 nm의 Zn 두께, 1 분의 황화공정 조건에서 제작된 ZnS 박막을 CIGS 태양전지의 버퍼층으로 적용한 결과, 반사방지막 없이 12.6%의 변환효율을 얻었다.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.3
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• pp.178-192
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• 2006

The buffer overflow attack is the single most dominant and lethal form of security exploits as evidenced by recent worm outbreaks such as Code Red and SQL Stammer. In this paper, we propose microarchitectural techniques that can detect and recover from such malicious code attacks. The idea is that the buffer overflow attacks usually exhibit abnormal behaviors in the system. This kind of unusual signs can be easily detected by checking the safety of memory references at runtime, avoiding the potential data or control corruptions made by such attacks. Both the hardware cost and the performance penalty of enforcing the safety guards are negligible. In addition, we propose a more aggressive technique called corruption recovery buffer (CRB), which can further increase the level of security. Combined with the safety guards, the CRB can be used to save suspicious writes made by an attack and can restore the original architecture state before the attack. By performing detailed execution-driven simulations on the programs selected from SPEC CPU2000 benchmark, we evaluate the effectiveness of the proposed microarchitectural techniques. Experimental data shows that enforcing a single safety guard can reduce the number of system failures substantially by protecting the stack against return address corruptions made by the attacks. Furthermore, a small 1KB CRB can nullify additional data corruptions made by stack smashing attacks with only less than 2% performance penalty.