• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1372-1382
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• 1999

The major source of errors in high-speed networks such as Broadband ISDN(B-lSDN) is buffer overflow during congested conditions. These congestion errors are the dominant sources of errors in 1high-speed networks and result in cell losses. Conventional communication protocols use error detection and retransmission to deal with lost packets and transmission errors. However, these conventional ARQ(Automatic Repeat Request) methods are not suitable for the high-speed networks since the transmission delay due to retransmissions becomes significantly large. As an alternative, we have presented a method to recover consecutive cell losses using forward error correction(FEC) in ATM(Asynchronous Transfer Mode)networks to reduce the problem. The performance estimation based on the cell discard process model has showed our method can reduce the cell loss rate substantially. Also, the performance estimations in ATM networks by interleaving and IP multicast service are discussed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1B
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• pp.1-12
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• 2002

In the multimedia CDMA mobile communication service, it is required to support various applications, such as voice, video, file transfer, e-mail, and Internet access, with guaranteed QoS. In the mixed traffic environment ,which consists of voice, stream data, and packet data, we analyze the network where preemptive priority is granted to delay-intolerant voice service and a buffer is offered to delay-tolerant stream data service. And, for best-effort packet data service, the access control by transmission permission probability is applied to obtain prominent throughput. To analyze the multimedia CDMA mobile communication system, we build a 2-dimensional markov chain model about prioritized-voice and stream data services and accomplish numerical analysis in combination with packet data traffic based on residual capacity equation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.1-8
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• 2004

This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.124-131
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• 2014

This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.55-60
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• 2014

For an high speed communication, a 40GHz VCO was implemented using a 0.11um standard CMOS technology. The mm-wave VCO was designed by a LC type using a spiral inductor, and a simplified architecture with buffers and a smart biasing technique were used to get a high performance. The frequency range of the proposed VCO is 34~40GHz which is suitable for mm-Wave communication system. It has an output power of -16dBm and 16% tuning range. And the phase noise is -100.33dBc/Hz at 1MHz offset at 38GHz fundamental frequency. The total power consumption of VCO including PADs is 16.8mW with 1.2V supply voltage. The VCO achieves the FOMT of -183.8dBc/Hz which is better than previous VOCs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1035-1044
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• 1998

A new multi-channel access scheme and the associated network architecture for a single-hop WDM local area network is proposed in this paper. The proposed architecture has Central Scheduling Node (CSN) for the transmission coordination among many users, which is one of the key issues in single-hop WDM networks. The data channels, source nodes, and destination nodes are selected at CSN in very simple menner. Our scheme can relive the control processing overhead at all nodes in the network which is caused in existing distributed scheduling algorithms. CSN is simple in the architecture can be implemented easily. in respect to the network performance, the maximum obtainable throughput is up to that of the ideal output queuing because of collision free scheduling. We use the MQMS (multi-queue multi-server) model for performance analaysis.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.111-120
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• 2001

VC merging involves distinguishing cells from an identical merged VC label. Various approaches have been proposed to help this identification process. However, most of them incur additional buffering, protocol overhead and/or variable delay. They make the provision of QoS difficult to achieve. So it was proposed a merge capable scheduler to support VC-merging (VCMS). However, in situations where all VCs are to be merged or the incoming traffic load is very low, it could happen that there are not enough non-merging cells to snoop. In this situation the scheduler uses special control cells to fill the empty time slots out. Too many control cells can cause high cell loss ratio and an additional packet transfer delay. To overcome the drawbacks, we propose a Sequence Skipping(SS) method where the sequencers skip the empty queues and insert SS cells. We show SS method is suitable for VC-merging and can reduce the cell loss ratio and the mean packet transfer delay through simulations.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.51.2-51.2
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• 2009

본 실험에서는 레이저 간섭 리소그래피를 이용한 2차원 나노 패턴을 형성하였고, 수열합성법을 이용하여 90 도에서 ZnO 나노 기둥을 ZnO/Si 기판 상에 제작 하였다. ZnO 버퍼층은 스퍼터를 이용하여 200도, Ar 분위기에서 증착 하였으며, 레이저 간섭 리소그래피를 이용하여 두 번의 노광을 통해 2차원 나노 패턴을 형성하였다. 먼저, 최적화된 포토레지스트를 ZnO/Si 기판 위에 도포하고, 2500rpm에서 30초간 스핀코팅 한 후, 첫번째 노광을 실시 하였고, ZnO/Si 기판을 회전시켜 첫번째 노광과 교차 시킨 다음 두 번째 노광을 통해 교차하는 부분만 현상되도록 하였다. 기판의 회전 및 기판과 입사 레이저 사이의 각도를 조절하여 제작된 나노 패턴의 종류는 square lattice, centered rectangular lattice, oblique lattice, hexagonal lattice, rectangular lattice, 5가지로, 2차원의 모든 격자를 제작 하였다. 저온 수열합성법에서는 Na citrate를 형상제어제 (surfactant ions)로 사용하여 ZnO 나노 기둥을 형성하였다. $NH_4OH$를 이용하여 용액의 pH를 조절하였고, Zn nitrate hexahydrate를 Zn의 원료 물질로 사용하였다. 2차원 나노 패턴의 3차원 형태는 Atomic force microscopy (AFM, Veeco instruments, USA)를 이용하여 접촉 모드에서 관찰하였고, ZnO 나노 구조는 주사 전자 현미경 (FE-SEM, Model: JSM-6701F, Tokyo, Japan) 를 통하여 분석 하였다. 나노 패턴의 AFM 분석 결과 ZnO/Si 기판상에 포토레지스트가 주기적인 배열을 가지는 것을 확인하였고, ZnO/Si 기판상에 포토레지스트가 완전히 현상된 부분이 일정한 배열을 가지는 것을 확인하였다. 포토레지스트가 현상되어 기판의 표면이 드러난 부분의 크기는 약 250nm로 측정되었다. ZnO 나노 구조의 FE-SEM 분석 결과, 각각의 나노 구조가 나노패턴 중 완전히 현상된 부분만을 통하여 성장되었다는 것을 확인하였고, 형상 제어제로 사용된 Na citrate의 첨가 여부에 따라 나노 구조의 모양이 변화되었다는 것을 알 수 있었다. Na citrate 가 첨가된 나노 기둥의 경우 약 500nm의 길이를 가지는 하나의 기둥 형태로 성장하였다는 것을 확인하였다.

• The KIPS Transactions:PartC
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• v.9C no.1
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• pp.65-72
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• 2002

In this paper, we implement a high-speed swatch tilth the function for label integration to enhance the expansion of networks using the label space of routers efficiently on MPLS over ATM networks. We propose an appropriate hardware structure to support the VC-merge function and differentiated services simultaneously. In this paper, we use the adaptive congestion control method such as EPD algorithm in carte that there is a possibility of network congestion in output buffers of each core LSR. In addition, we justify the validity of the proposed VC-merge method through simulation and comparison to conventional Non VC-merge methods. The proposed VC-merge capable switch is modeled in VHDL. synthesized, and fabricated using the SAMSUNG 0.5um SOG process.