• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.66-75
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• 2016

Due to aggressive scaling of device sizes and reduced noise margins, physical defects caused by aging and process variation are continuously increasing. Additionally, with scaling limitation of metal wire and the increasing of communication volume, fault tolerant method in manycore network-on-chip (NoC) has been actively researched. However, there are few researches investigating reliability in NoC with voltage-frequency-island (VFI) regime. In this paper, we propose a table-based routing technique that can communicate, even if link failures occur in the VFI NoC. The output port is alternatively selected between best and the detour routing path in order to improve reliability with minimized hardware cost. Experimental results show that the proposed method achieves full coverage within 1% faulty links. Compared to $d^2$-LBDR that also considers a routing method for searching a detour path in real time, the proposed method, on average, produces 0.8% savings in execution time and 15.9% savings in energy consumption.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.41-48
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• 2018

The quantitative interfacial adhesion energy measurement method of copper redistribution layer and WPR dielectric interface were investigated using $90^{\circ}$ peel test, 4-point bending test, double cantilever beam (DCB) measurement for FOWLP Applications. Measured interfacial adhesion energy values of all three methods were higher than $5J/m^2$, which is considered as a minimum criterion for reliable Cu/low-k integration with CMP processes without delamination. Measured energy values increase with increasing phase angle, that is, in order of DCB, 4-point bending test, and $90^{\circ}$ peel test due to increasing roughness-related shielding and plastic energy dissipation effects, which match well interfacial fracture mechanics theory. Considering adhesion specimen preparation process, phase angle, measurement accuracy and bonding energy levels, both DCB and 4-point bending test methods are recommended for quantitative adhesion energy measurement of RDL interface depending on the real application situations.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.123-123
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• 2000

선폭이 초미세화됨에 따라 게이트 전극에서의 공핍 현상 및 불순물 확산의 물제를 갖는 poly-Si 게이트를 대체할 전극 물질로 텅스텐(W)이 많이 연구되어 왔다. 반도체 소자의 배선물질로 일찍부터 사용되어온 텅스텐은 내화성 금속의 일종으로 용융점이 높고, 저항이 낮다. 그러나, 일반적으로 사용되고 있는 CVD에 의한 텅스텐의 증착은 반응가스(WF6)로부터 오는 불소(F)의 게이트 산화막내로의 확산으로 인해 MOS 소자가 크게 열화될수 있다. 본 연구에서는 W/TiN 이중 게이트 전극 구조를 갖는 MOS 캐패시터를 제작하여 전기적 특성을 살펴보았다. P-Type (100) Si위에 RTP를 이용, 85$0^{\circ}C$에서 110 의 열산화막을 성장 및 POA를 수행한 후, 반응성 스퍼터링법에 의해 상온, 6mTorr, N2/Ar=1/6 sccm, 100W 조건에서 TiN 박막을 150, 300, 500 의 3그룹으로 증착하였다. 그 위에 LPCVD 방법으로 35$0^{\circ}C$, 0.7Torr, WF6/SiH4/H2=5/5~10/500sccm 조건에서 2000~3000 의 텅스텐을 증착하였다. Photolithography 공정 및 습식 에칭을 통해 200$\mu\textrm{m}$$\times$200$\mu\textrm{m}$ 크기의 W/TiN 복층 게이트 MOSC를 제작하였다. W/TiN 복측 게이트 소자와 비교분석하기 위해 같은 조건의 산화막을 이용한 알루미늄(Al) 게이트, 텅스텐 게이트 MOSC를 제작하였다. 35$0^{\circ}C$에서 증착된 텅스텐 박막은 10~11$\Omega$/ 의 면저항을 가졌고 미소한 W(110) peak값을 나타내는 것으로 보아 비정질 상태에 가까웠다. TiN 박막의 경우 120~130$\Omega$/ 의 면저항을 가졌고 TiN (200)의 peak 값이 크게 나타난 반면, TiN(111) peak가 미소하게 나타났다. TiN 박막의 두께와 WF/SiH4의 가스비를 변화시켜가며 제작된 MOS 캐패시터를 HF 및 QS C-V, I-V 그리고 FNT를 통한 전자주입 방법을 이용하여 TiN 박막의 불소에 대한 확산 방지막 역할을 살펴 보았다. W/TiN 게이트 MOS 소자는 모두 순수 텅스텐 게이트보다 우수하였고, Al 게이트와 유사한 전기적 특성을 보여주었다. W/TiN 게이트 MOS 소자는 모두 순수 텅스텐 게이트보다 우수하였고, Al 게이트와 유사한 전기적 특성을 보여주었다. TiN 박막이 300 , 500 이고 WF6/SiH4의 가스비가 5:10인 경우 소자 특성이 우수하였으나, 5:5의 경우에는 FNT 전자주입 특성이 열화되기 시작하였다. 그리고, TiN박막의 두께가 150 으로 얇아질 경우에는 WF6/SiH4의 가스비가 5:10인 경우에서도 소자 특성이 열화되기 시작하였다. W/TiN 복층 게이트 MOS 캐패시터를 제작하여 전기적인 특성 분석결과, 순수 텅스텐 게이트 소자의 큰 저전계 누설 전류 특성을 해결할 수 있었으며, 불소확산에 영향을 주는 조건이 WF6/SiH4의 가스비에 크게 의존됨을 알 수 있었다. TiN 박막의 증착 공정이 최적화 될 경우, 0.1$\mu\textrm{m}$이하의 초미세소자용 게이트 전극으로서 텅스텐의 사용이 가능할 것으로 보여진다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.22 no.1
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• pp.5-10
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• 2012

In general, the fabrications of the LEDs with mesa structure are performed grown by MOCVD method. In order to etch and separate each chips, the LEDs are passed the RIE and scribing processes. The RIE process using plasma dry etching occur some problems such as defects, dislocations and the formation of dangling bond in surface result in decline of device characteristic. The SAG method has attracted considerable interest for the growth of high quality GaN epi layer on the sapphire substrate. In this paper, the SAG method was introduced for simplification and fabrication of the high quality epi layer. And we report that the size of selective area do not affect the characteristics of original LED. The diameter of SAG circle patterns were choose as 2500, 1000, 350, and 200 ${\mu}m$. The SAG-LEDs were measured to obtain the device characteristics using by SEM, EL and I-V. The main emission peaks of 2500, 1000, 350, and 200 ${\mu}m$ were 485, 480, 450, and 445 nm respectively. The chips of 350, 200 ${\mu}m$ diameter were observed non-uniform surface and resistance was higher than original LED, however, the chips of 2500, 1000 ${\mu}m$ diameter had uniform surface and current-voltage characteristics were better than small sizes. Therefore, we suggest that the suitable diameter which do not affect the characteristic of original LED is more than 1000 ${\mu}m$.

• Korean Chemical Engineering Research
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• v.45 no.5
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• pp.466-472
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• 2007

A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.1-7
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• 2021

In this paper, by embedding a bare-die chip-type drive amplifier into the PCB composed of ABF and FR-4, it implements an embedded active device that can be applied in 28 GHz band modules. The ABF has a dielectric constant of 3.2 and a dielectric loss of 0.016. The FR-4 where the drive amplifier is embedded has a dielectric constant of 3.5 and a dielectric loss of 0.02. The proposed embedded module is processed into two structures, and S-parameter properties are confirmed with measurements. The two process structures are an embedding structure of face-up and an embedding structure of face-down. The fabricated module is measured on a designed test board using Taconic's TLY-5A(dielectric constant : 2.17, dielectric loss : 0.0002). The PCB which embedded into the face-down expected better gain performance due to shorter interconnection-line from the RF pad of the Bear-die chip to the pattern of formed layer. But it is verified that the ground at the bottom of the bear-die chip is grounded Through via, resulting in an oscillation. On the other hand, the face-up structure has a stable gain characteristic of more than 10 dB from 25 GHz to 30 GHz, with a gain of 12.32 dB at the center frequency of 28 GHz. The output characteristics of module embedded into the face-up structure are measured using signal generator and spectrum analyzer. When the input power (P_in) of the signal generator was applied from -10 dBm to 20 dBm, the gain compression point (P_1dB) of the embedded module was 20.38 dB. Ultimately, the bare-die chip used in this paper was verified through measurement that the oscillation is improved according to the grounding methods when embedding in a PCB. Thus, the module embedded into the face-up structure will be able to be properly used for communication modules in millimeter wave bands.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.21 no.3
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• pp.114-118
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• 2011

We report on the growth and characterization of nano and micro scale GaN structures selectively grown on the vertex of hexagonal GaN pyramids. $SiO_2$ near the vertex of hexagonal GaN pyramids was removed by optimized photolithgraphy process and followed by a selective growth of nano and micro scale GaN structures by metal organic vapor phase epitaxy (MOVPE). The pyramidal GaN nano and micro structures which have crystal facets of semi-polar {1-101} facets were formed only on the vertex of GaN pyramids and the size of the selectively grown nano and micro GaN structures was easily controlled by growth time. As a result of TEM measurement, Reduction of threading dislocation density was conformed by transmission electron microscopy (TEM) in the selectively grown nano and micro GaN structures. However, stacking faults were newly developed near the edge of $SiO_2$ film because of the roughness and nonuniformity in thickness of the $SiO_2$ film.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.21 no.3
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• pp.110-113
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• 2011

In this paper, we propose a new method for the fabrication of GaN microstructures formed only on the vertex of GaN pyramid by using of metal catalysts. GaN pyramidal structures were selectively grown on 3 ${\mu}m$ $SiO_2$ dot patterns followed by thin film deposition of Au and Cr only on the vertex area of the GaN pyramids with precisely controlled photolithography. After the metal deposition, the samples were loaded in the MOVPE reactor for the growth of GaN microstructures for 10 minutes. Temperature for the growth of the GaN microstructures was changed from $650^{\circ}C$ to $750^{\circ}C$. Rod type GaN microstructures were grown in the direction of vertical to the six {1-101} facets and the shape of the GaN microstructures was changed depend on the type of metal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.