• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.164-165
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• 2008

현재의 소자간 연결을 위해 사용되는 금속배선 PCB의 한계로 인해 보다 고속/대용량의 광PCB가 크게 각광받고 있다. 본 논문에서는 광PCB와 소자간의 전기적 연결을 위해 사용되는 솔더 범프를 전도성 에폭시를 사용하여 마이크로 머시닝 공정을 통해 구현하고 제작된 솔더 범프의 I-V 특성을 살펴보았다. 제작된 100 um $\times$ 100 um $\times$ 25 um 와 300 um $\times$ 300 um $\times$ 25 um 의 샘플에서 각각 30 m$\Omega$과 90m$\Omega$의 전기저항을 얻을 수 있었다. 이를 통해 향후 센서및 엑츄에이터 시스템과 광 MEMS 등의 여러 분야에서 전도성 에폭시 솔더 범프를 이용하여 우수한 성능의 플립칩 본딩을 구현할 수 있을 것이다.

• Journal of the Semiconductor & Display Technology
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• v.10 no.2
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• pp.73-81
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• 2011

We manufactured the inkjet printing system for the application into the nano Ag finger line interconnection process in Si solar cells. The home-made inkjet printer consists of motion part for XY motion stage with optical table, head part, power and control part in the rack box with pump, and ink supply part for the connection of pump-tube-sub ink tanknozzle. The ink jet printing system has been used to conduct the interconnection process of finger lines on Si solar cell. The nano ink includes the 50 nm-diameter. Ag nano particles and the viscosity is 14.4 cP at $22^{\circ}C$. After processing of inkjet printing on the finger lines of Si solar cell, the nano particles were measured by scanning electron microscope. After the heat treatment at $850^{\circ}C$, the finger lines showed the smooth surface morphology without micropores.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1313-1323
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• 1991

n this thesis CAM(content Addressable Memory) generator and graphic display tool for run-plot sequence in automatic generation of CAM are presented. We show that implementing the layout generation, graphic menu, mouse driver, and data structure by using the basic classes is clear and easy in modification than the conventional procedural language. For the implementation of generator which is independent of design rule or process, we use the parameterized cell so that basic cell can be changed according to user's inputs. and perform the layout by means of placement and routing using pitch mathching. Finally, the display of CIF which generated and constitution of graphic menu for total run-plot sequence are explained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.531-536
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• 2009

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.173-174
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• 2007

반도체 소자가 발달함에 따라서 박막은 더욱 다층화 되고 그 두께는 줄어들고 있다. 따라서 소자의 초고집적화를 위해서는 각 박막의 두께를 더욱 작게 하여야 한다. 또한 반도체 소자 제조 공정에서는 Si 기판과 금속 박막간의 확산이 커다란 문제로 부각되어 왔다. 특히 Cu는 높은 확산성에 의하여 Si 기판과 접합에서 많은 확산에 의한 문제가 발생하게 되며, 또한 선폭이 줄어듦에 따라 고열이 발생하여 실리콘으로 spiking이 발생하게 된다. 이러한 확산을 방지하기 위하여 금속 배선과 Si기판 사이에는 필연적으로 확산방지막을 삽입하게 되었다. 기존의 연구에서는 $1000\;{\AA}$의 W-B-C-N 확산방지막을 제작하여 연구하였다. 이 논문에서는 Cu의 확산을 방지하기 위한 W-B-C-N 확산방지막을 다양한 두께로 제작하여 그 특성을 확인하여 초고집적화를 위한 더욱 얇은 두께의 W-B-C-N 확산방지막에 대하여 연구하였다. W-B-C-N 확산방지막의 두께 변화에 대한 특성을 확인하기 위하여 $900^{\circ}C$까지 열처리 한 후 그 면저항을 측정하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.179-179
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• 1998

실리콘 집적회로 제조시 sub-micron 의 contact 형성 공정은 질연막 형성 후 이의 식각 및 세정, c contact 실리사이드, 획산방지막, 배선 금속층의 형성 과정올 거치게 된다. 본 연구팀에서는 C.F야f2 헬리 콘 플라즈마훌 이용한 고선택비 contact 산화막 식각공정시 형성된 잔류막충과 오염 손상올 관찰하고 산소 플라즈마 처리와 후속 열처리에 따른 이들의 제거 정도를 관찰하여 이에 대한 결과를 발표하였다. 본 연구메서는 식각 및 후처리에 따라 잔류하는 잔류막과 손상층이 후속 공정인 contact 실리사이드 형 섬에 미치는 영향올 관찰하였다. C C.F바f2 웰리콘 풀라즈마률 이용한 식각시 공정 변수로는 수소가스 첨가, bias voltage 와 과식각 시간 의 효과를 관찰하였으며 다른 조건은 일정하게 하였다 .. Contact 실리사이드로는 Ti, Co-싫리사이드를 선 택하였으며 Piranha cleaning, 산소 플라즈마 처리, 산소 풀라즈마+600 'C annealing으로 각각 후처리된 시 편을 후처리하지 않은 시펀돌과 함께 실리사이드 형성용‘시펀으로 이용하였다 각각 일정 조건에서 동 일 두께의 실리사이드훌 형성시킨 후 4-point probe룰 이용하여 면저황올 측정하였다 후처리하지 않은 시편의 경무 실리사이드 형성은 아주 시펀의 일부분에서만 형성되었으며 후속 세정 및 얼처리훌 황에 따라 실리사이드의 면저항은 감소하여 식각 과정을 거치지 않은 깨끗한 실리콘 웨이퍼위에 실리사이드 를 형성시킨 값(control 값)에 접근하였다. 실리사이드의 면저항값은 식각시 노훌된 실리콘 표면 위에 형 성된 손상충보다는 잔류막에 큰 영향을 받았으며 수소 가스가 첨가된 식각 가스로 식각한 시편으로 형 성한 실리사이드의 면저항값이 손상이 상대적으로 적은 것으로 관찰된 수소훌 첨가하지 않은 식각 가 스로 식각한 시펀 위에 형성된 실리사이드의 면저황에 비해 낮은 값을 나타내었다. 실리사이드의 전기적 륙성에 미치는 손상층의 영향올 좀더 면밀히 관찰하고자 bare 실리콘 wafer 에 잔류막이 거의 없이 손상층을 유발시키는 식각 조건들 (100% HBr, 100%H2, 100%Ar, Cl싸fz)에 대하여 실 리콘 식각을 수행한 후 Co-실리사이드률 형성하여 이의 면저황을 측정한 걸과 100% Ar 가스로 식각된 시편을 이용하여 형성한 실리사이드의 면저항은 control 에 기까운 면저항값올 지니고 따라서 손상층이 실리사이드 형섬메 미치는 영향은 크지 않음을 알 수 있었다. 이상의 연구 결과훌 통해 손상층이 실리사이드의 형성이나 전기적 톡섬에 미치는 영황은 잔류막층 에 의한 영향보다 적다는 것을 알 수 았으며 잔류막층의 두께보다는 성분이나 걸합상태, 특히 식각 및 후처리 후 잔류하는 탄소 싱분과 C-Si 결함에 큰 영향올 받는 것올 알 수 있었다.

• Clean Technology
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• v.16 no.2
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• pp.103-116
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• 2010

It has been reported that the LCD panel market in the FPD industry is become growing and its panel size and production capacity are increasing, and its manufacturing technique is improved every year. FPD manufacturing process requires high cleanliness in its overall process. Especially, FPD cleaning process which accounts for 30~40% of total manufacturing process is very important in its technological and productivity aspects. It is difficult to remove residual liquid-crystal in the fine gap after liquid-crystal injection process in the cell. In this study, aqueous cleaning agents with excellent cleaning, rinsing, and penetrating abilities, but minimum ion content for LCD panel were formulated through mixing glycol ether-type and glycol dimethyl ether-type solvents and nonionic surfactants which are widely used as raw materials for alternative cleaning agents because of environmental regulation at home and abroad. And the formulated cleaning agents were applied to clean FPD liquid crystal after its injection in the cell. Physical properties, cleaning efficiencies, and rinsabilities of the formulated cleaning agents with different combination ratios of solvents, surfactants and additives were measured. As experimental results, the formulated cleaning agents showed higher wetting indices and cloud point than the traditional commercial cleaning agent. And it was found that cleaning efficiencies of the formulated cleaning agents were influenced by the structure of main solvents in them and the types of liquid crystal as soil for cleaning. The best cleaning agents among the formulated cleaning agents showed similar cleaning efficiencies and better rinsabilities compared to the conventional cleaning agent.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.49-55
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• 2016

The effects of post-annealing and temperature/humidity conditions on the interfacial adhesion energies of atomic layer deposited RuAlO diffusion barrier layer for Cu interconnects were systematically investigated. The initial interfacial adhesion energy measured by four-point bending test was $7.60J/m^2$. The interfacial adhesion energy decreased to $5.65J/m^2$ after 500 hrs at $85^{\circ}C$/85% T/H condition, while it increased to $24.05J/m^2$ after annealing at $200^{\circ}C$ for 500 hrs. The X-ray photoemission spectroscopy (XPS) analysis showed that delaminated interface was RuAlO/$SiO_2$ for as-bonded and T/H conditions, while it was Cu/RuAlO for post-annealing condition. XPS O1s peak separation results revealed that the effective generation of strong Al-O-Si bonds between $AlO_x$ and $SiO_2$ interface at optimum post-annealing conditions is responsible for enhanced interfacial adhesion energies between RuAlO/$SiO_2$ interface, which would lead to good electrical and mechanical reliabilities of atomic layer deposited RuAlO diffusion barrier for advanced Cu interconnects.

• Journal of the Korean Vacuum Society
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• v.18 no.3
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• pp.203-207
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• 2009

Copper is known as a replacement for aluminum wire which is used for semiconductor. Because specific resistance of Cu ($1.67{\mu}{\Omega}$-cm) is lower than that of Al ($2.66{\mu}{\Omega}$-cm), Cu reduce RC delay time. Although melting point of Cu($1085^{\circ}C$) is higher than melting point of Al, Cu have characteristic to easily react with Silicon(Si) in low temperature, and it isn't good at adhesive strength with Si. For above these reason, research of diffusion barrier to prevent reaction between Cu and Si and to raise adhesive strength is steadily advanced. Our study group have researched on W-C-N (tungsten-carbon-nitrogen) Diffusion barrier for preventing diffusion of Cu through semiconductor. By recent studies, It's reported that W-C-N diffusion barrier can even precent Cu and Si diffusing effectively at high temperature. In this treatise, we vaporized different proportion of N into diffusion barrier to research Cu's Electromigration based on the results and studied surface hardness in the heat process using nano scale indentation system. We gain that diffusion barrier containing nitrogen is more stable for Cu's electromigration and has stronger surface hardness in heat treatment process.

• Korean Journal of Materials Research
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• v.1 no.1
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• pp.46-53
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• 1991

The stress of PSG (Phosphosilicate glass), USG (Undoped-silicate grass) and SiN films, which are mainly used as passivation layers in semiconductor memory devices, deposited by CVD methods has been studied as a function of film thickness and holding time in air. The stress of the PSG film or the USG film is increased in tensile state with increasing film thickness. On the other hand the stress level of the SiN film in compressive stress does not change as film thickness changes. The stress of PSG film shows the drastic change from the tensile stress to the compressive stress after the film is left 2 days in air. FTIR spectra indicated that the stress variation was due to the penetration of water molecule. It looks possible to recover the stress of about $2.5{\times}{10^9}dyne/cm^2$ by annealing treatment at $300^{\circ}C$ for 20min. The total stress of multi-layered films having the PSG film is determined mainly by the stress variation of PSG layer with holding time. The total stress of multi-layered film appears to have a functional relationship with the stress in the thickness of each film. The resistance against stress-migration of sputtered Al line increases with increasing the tensile stress for the PSG film or the USG film.