• Journal of the Institute of Convergence Signal Processing
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• v.2 no.2
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• pp.62-67
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• 2001

In the recent mobile communication systems, the performance of Turbo Code using the error correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the turbo decoder. However, performance depends on the interleaver depth that need a large time delay over the reception process. Moreover, Turbo Code has been known as the robust ending method with the confidence over the fading channel. The International Telecommunication Union(ITU) has recently adopted as the standardization of the channel coding over the third generation mobile communications such as IMT-2000. Therefore, in this paper, we proposed of the method to improve the conventional performance with the parallel concatenated 4-New Turbo Decoder using MAP a1gorithm in spite of complexity increasement. In the real-time video and video service over the third generation mobile communications, the performance of the proposed method was analyzed by the reduced decoding delay using the variable decoding method by computer simulation over AWGN and fading channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.187-198
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• 2004

In this paper, we analyze the performance of BPM (Bi-Phase Modulation) UWB (Ultra Wide Band) multiple access system using PN (Pseudo Noise) code based time hopping sequence in indoor wireless channels. In particular, we compare BPM UWB multiple access system with PPM (Pulse Position Modulation) UWB multiple access system in terms of signalling and demodulation schemes. Moreover, we analytically evaluate the performance of these UWB systems by deriving the bit error rate expressions under the assumption that pulse energy and data transmission rate are identical for both systems. Simulation results in additive white Gaussian noise and realistic indoor multipath wireless channels show that the performance of BPM scheme is approximately 1 dB better than that of PPM scheme. However, the performance discrepancy becomes negligible as the number of users increases.

• Journal of Digital Convergence
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• v.12 no.3
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• pp.269-275
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• 2014

The DAB system was designed to provide CD quality audio and data services for fixed, portable and mobile applications with the required BER below $10^{-4}$. However for the T-DMB system with the video service of MPEG-4 stream, BER should go down $10^{-8}$ by adding FEC blocks which consist of the Reed-Solomon (RS) encoder/decoder and convolutional interleaver/deinterleaver. In this paper we propose two types of turbo coded T-DMB system without altering the puncturing procedure and puncturing vectors defined in the standard T-DMB system for compatibility. One(Type 1) can replace the existing RS code, convolutional interleaver and RCPC code by a turbo code and the other one (Type 2) can substitute the existing RCPC code by a turbo code. Simulation results show that two new turbo coded systems are able to yield considerable performance gain after just 2 iterations. Type 2 system is better than type 1 but the amount of performance improvement is small.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.13-16
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• 2000

In the recent mobile communication systems, the performance of Turbo Code using the error correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the turbo decoder. However, performance depends on the interleaver depth that need great many delay over the reception process. Moreover, Turbo Code has been known as the robust coding methods with the confidence over the fading channel. The International Telecommunication Union(ITU) has recently adopted as the standardization of the channel coding over the third generation mobile communications the same as IMT-2000. Therefore, in this paper, we proposed of that has the better performance than existing Turbo Decoder that has the parallel concatenated four-step structure using MAP algorithm. In the real-time voice and video service over the third generation mobile communications, the performance of the proposed method was analyzed by the reduced decoding delay using the variable decoding method by computer simulation over AWGN and lading channels.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2375-2381
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• 2014

In case the coefficient set of an FIR filter is represented in the canonic signed digit (CSD) format with a few nonzero digits, it is possible to implement high data rate digital filters with low hardware cost. Designing an FIR filter with CSD format coefficients, whose number of nonzero signed digits is minimal, is equivalent to finding sparse nonzero signed digits in the coefficient set of the filter which satisfies the target frequency response with minimal maximum error. In this paper, a compressive sensing based CSD coefficient FIR filter design algorithm is proposed for multiplierless and high speed implementation. Design examples show that multiplierless FIR filters can be designed using less than two additions per tap on average with approximate frequency response to the target, which are suitable for high speed filtering applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.401-404
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• 2016

This paper proposes entropy coding method of HEVC CABAC Encoder for efficient hardware architecture. The Binary Arithmetic Encoder requires data dependency at each step, which is difficult to be operated in a fast. Proposed Binary Arithmetic Encoder is designed 4 stage pipeline to quickly process the input value bin. According to bin approach, either MPS or LPS is selected and the binary arithmetic encoding is performed. Critical path caused by repeated operation is reduced by using the LUT and designed as a shift operation which decreases hardware size and not using memory. The proposed Binary Arithmetic Encoder of CABAC is designed using Verilog-HDL and it was implemented in 65nm technology. Its gate count is 3.17k and operating speed is 1.53GHz.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.635-646
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• 2011

In distributed video coding, low complexity encoder can be realized by shifting encoder-side complex processes to decoder-side. However, not only motion estimation/compensation processes but also complex LDPC decoding process are imposed to the Wyner-Ziv decoder, therefore decoder-side complexity has been one important issue to improve. LDPC decoding process consists of numerous iterative decoding processes, therefore complexity increases as the number of iteration increases. This iterative LDPC decoding process accounts for more than 60% of whole WZ decoding complexity, therefore it can be said to be a main target for complexity reduction. Previously, HDA (Hard Decision Aided) method is introduced for fast LDPC decoding process. For currently received parity bits, HDA method certainly reduces the complexity of decoding process, however, LDPC decoding process is still performed even with insufficient amount of parity request which cannot lead to successful LDPC decoding. Therefore, we can further reduce complexity by avoiding the decoding process for insufficient parity bits. In this paper, therefore, a parity request estimation method is proposed using bit plane-wise correlation and temporal correlation. Joint usage of HDA method and the proposed method achieves about 72% of complexity reduction in LDPC decoding process, while rate distortion performance is degraded only by -0.0275 dB in BDPSNR.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.8C
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• pp.522-528
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• 2011

The iterative detection and decoding (IDD) has been shown to dramatically improve the bit error rate (BER) performance of the multiple-input multiple-output (MIMO) communication systems. However, these techniques require a high computational complexity since it is required to compute the soft decisions for each bit. In this paper, we show IDD comprised of sphere decoder with low-density parity check (LDPC) codes and present the tree search strategy, called a layer symbol search (LSS), to obtain soft decisions with a low computational complexity. In addition, an adaptive early termination is proposed to reduce the computational complexity during an iteration between an inner sphere decoder and an outer LDPC decoder. It is shown that the proposed approach can achieve the performance similar to an existing algorithm with 70% lower computational complexity compared to the conventional algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.67-74
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• 2007

Turbo code, a kind of channel coding technique, has ben used in the field of digital mobile communication system if the number of iterations is increased in the several channel environments, my further iteration results in very little improvement, and requires much delay and computation in proportion to the number of iterations. In this paper, it proposes an efficient stopping rules for the iteration process in turbo decoding. By using absolute mean values for the LLR difference values between the first and second decoder in the present decoding process, the proposed algorithm can largely reduce the average number of iterations without BER performance degradation in all SNR regions. As a result of simulation, the average number of iterations of proposed algorithm is reduced by about $18.25%{\sim}20.58%$ compared to SDR algerian in the lower SNR region, and is reduced by about $22.96%{\sim}28.74%$ compared to method using variance values of extrinsic information in the upper SNR region.