• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.05a
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• pp.251-254
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• 2006

In this paper, cutting qualifies and fracture strength of silicon dies by laser dicing are investigated. Laser micromachining is the non-contact process using thermal ablation and evaporation mechanisms. By these mechanisms, debris is generated and stick on the surface of wafer, which is the problem to apply laser dicing to semiconductor manufacture process. Unlike mechanical sawing using diamond blade, chipping on the surface and crack on the back side of wafer isn't made by laser dicing. Die strength by laser dicing is measured via the three-point bending test and is compared with the die strength by mechanical sawing. As a results, die strength by the laser dicing shows a decrease of 50% in compared with die strength by the mechanical sawing.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.05a
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• pp.211-215
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• 2006

평면 광도파로 코어로 사용되는 SiON (Silicon oxynitride)과 클래딩으로 사용되는 $SiO_2$ (Silicon oxide)의 굴절률 차이가 2.5 %인 고굴절률차 평면 광도파로용 SiON 박막을 PECVD (plasma enhanced chemical vapor deposition)로 제작하였다. PECVD에 사용된 가스는 $SiH_4,\;NH_3,\;N_{2}O$이고, Si 기판의 $SiO_2$ 막은 100 nm이다. 가스의 비율에 따라 SiON 막의 굴절률은 633 nm의 파장에서 1.476에서 1.777까지 변화하였다. 코어로 사용되는 SiON의 두께는 $2.5{\mu}m$이고 클래딩과의 굴절률 차이는 2.5 %였다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.05a
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• pp.216-220
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• 2006

평면 광 신호 분리기와 광 케이블의 정밀결합을 위하여 V-groove를 제작하였다. V-groove 는 실리콘웨이퍼 (100) 면을 KOH 용액으로 선택적 습식 식각하여 제작되었다. V-groove 를 효과적으로 제작하기 위하여 KOH 의 조성 (10, 20, 30, 33, 40 wt%)과 온도 (50, 60, 70, $80^{\circ}C$)를 변화시켜 식각률과 표면조도를 측정하였다. 식각률은 $80^{\circ}C$에서 20 wt.% KOH 로 식각했을 경우 $1.84{\mu}m/min$ 로 가장 빨랐으며, 표면조도는 $80^{\circ}C$에서 33 wt.% KOH로 식각했을 경우 1.6nm로 가장 양호하였다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.05a
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• pp.221-224
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• 2006

이온주입으로 비정질화된 실리콘의 재결정화 및 활성화에 대한 실험을 전기로를 이용하여 수행하였다. 비정질 실리콘이 결정화 및 활성화가 이루어지면 전계효과 이동도가 좋아진다. 이동도가 향상되면 저항이 작아지고, 이로 인하여 소자의 크기가 작아질 수 있어 소형화가 가능해진다. 결정화 정도를 확인하는 방법으로 Four point probe를 이용한 면저항 측정과 라만 peak 측정을 이용하였다. 이온주입 후 비정질화된 실리콘의 재결정화를 통해서는 $600\;^{\circ}C$에서 1시간 열처리한 값이 가장 많이 결정화가 되었다는 것을 알 수 있었다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.05a
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• pp.202-205
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• 2006

Recently, high vacuum pumps are widely used in the semi-conduction and liquid-crystal display ( LCD ) process. The composite-type high vacuum pumps are widely used in the various processes. In this study, the pumping performance of composite-type molecular pumps has been investigated experimentally. The experimented pumps are a compound molecular pump ( CMP ) and hybrid molecular pump ( HMP ). The CMP consists with helical-type drag pump, at lower part, and with turbomolecular pump ( TMP ), at upper part. The HMP consists with disk-type drag pump, at lower part, and with TMP, at upper part. The experiments are performed in the outlet pressure of $0.2\;{\sim}\;533\;Pa$. We have measured the ultimate pressure, compression ratio, and pumping speed

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.05a
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• pp.206-210
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• 2006

본 논문에서는 HDPCVD를 이용한 실리콘 산화막 형성에서 산화막의 특성에 영향을 미치는 RF Power, Gas, 산소 등의 공정조건과 증착된 산화막의 특성을 나타내는 증착율, 균일성 및 굴절율에 관한 주효과와 교호작응을 정량적으로 규명하고, 산화막 증착에서 관심의 대상이 되는 여러가지의 반응변수를 모두 만족시키는 최적의 공정조건을 제시한다. 실험의 효율성을 높이기 위해 통계적인 실험계획법을 활용하여 실험의 회수를 줄이는 한편 반응모델링을 통하여 입력변수와 반응변수의 관계를 시각적으로 도식화 한다. 실험을 통하여 현재 사용되고 있는 공정조건에 대한 개선점을 발견하였으며, 수립된 모델을 바탕으로 한 반응최적화 알고리즘을 통하여 세 가지 반응변수 모두 만족시킬 수 있는 5가지의 입력조건을 제시한다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.05a
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• pp.194-197
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• 2006

Lead-free bismuth-layered perovskite ferroelectric europium-substituted $Bi_{4}Ti_{3}O_{12}(BTO)$ thin films have been successfully deposited on Pt/Ti/$SiO_2$/Si substrate by a sol-gel spin-coating process. $Bi(TMHD)_3,\;Eu(THMD)_3,\;Ti(OiPr)_4$ were used as the precursors, which were dissolved in 2-methoxyethanol. The thin films were annealed at various temperatures from $600^{\circ}\;to\;720^{\circ}C$ in oxygen ambient for 1 hr, which was followed by post-annealed for 1 hr after depositing a Pt electrode to enhance the electrical properties. X-ray diffraction (XRD) and scanning electron microscopy (SEM) were used to analyze the crystallinity and surface morphology of layered perovskite phase, respectively. The remanent polarization value of the BET thin films annealed at $720^{\circ}C\;was\;25.95{\mu}C/cm^2$ at an applied voltage of 5 V.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.192-200
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• 2005

A high speed address recovery technique for AC plasma display panel(PDP) is proposed. By removing the GND switching operation, the recovery speed can be increased and switching loss due to GND switch also becomes to be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Thus, th e technique shows the minimum address power consumption according to various displayed images, different from prior methods operating in fixed mode regardless of images. Test results with 50' HD single- scan PDP(resolution : $1366{\times}768$) show that less than 350ns of recovery time is successfully accomplished and about $54\%$ of the maximum power consumption can be reduced, tracing minimum power consumption curves.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.208-214
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• 2005

A number of watermark insertion method is proposed for the protection of audio contents such as MP3 music. In this paper, we propose a VLSI architecture that performs embedding watermark to the audio signal based on the scheme that proposed by XUEYAO LI[1]. This architecture is implemented and simulated in Verilog HDL. This watermark embedding method used a visually recognizable binary image. Despite a unit that determines the watermark embedded intensity is removed to archive low complexity of H/W, our experimental results show that watermarked signal is perceptually transparency and robust to several known attacks.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.215-218
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• 2005

Co-interlayer와 $SiO_2$ 상부막이 nickel germanosilicide 박막의 열안정성에 미치는 영향을 연구하였다. Nickel germanosilicide는 SiGe 기판 위에 Ni(8nm)/TiN(25nm), Ni(6m)/Co(2nm)/TiN(25nm)을 증착하여 각각 one step RIP($500^{\circ}C$)와 two step RTP(500. $700^{\circ}C$)로 형성되었다. 50과 10nm 두께의 $SiO_2$ 박막을 실리사이드 위에 증착하고, 550, 600, $650^{\circ}C$에서 30분간 열처리한 후 면저항 값을 측정하여 열안정성을 평가하였다.