• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.45-51
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• 2010

The main issue in mobile cloud computing is how to support a seamless service to a mobile mode. Mobile IPv6 (MIPv6) is a mobility supporting protocol which is standardized by the Internet Engineering Task Force (IETF). Mobile IPv6 fast handovers (FMIPv6) is the extension of MIPv6 which is proposed to overcome shortcomings of MIPv6. Recently, fast handovers for Mobile IPv6 over IEEE 802.16e which is one of broadband wireless access systems has been proposed by the IETF. It was designed for supporting cross-layer fast handover. In this paper, we propose an enhanced cross-layering mobile IPv6 fast handover over IEEE 802.16e networks. In our scheme, a new access router generates a new address for the mobile node by using a layer 2 trigger. We utilize a layer 2 message which is sent from a new base station to the new access router in order to inform the new access router of information of the mobile node. A previous access router sends a binding update message to the mobile node's home agent when it acquires the new address of the mobile node. We evaluate the performance of the proposed scheme compared with the existing schemes in terms of the signaling cost and the handover latency. From the results, we observe that the proposed scheme can support fast handover effectively over IEEE 802.16e networks than existing schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.