• Proceedings of the Korea Information Processing Society Conference
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• 2003.05c
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• pp.1575-1578
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• 2003

이동통신 기술의 발달로 인하여 무선 이동 기기의 사용이 보편화되면서 LBS(Location Based System)의 요구가 나날이 증대되고 있다. 이와 같은 위치 기반 서비스에서 클라이언트인 이동체들은 일정한 보고 주기를 가지고 서버에 위치 데이터를 보고하게 되는데, 빈번한 보고 데이터를 실시간으로 처리하기 위해서 서버에서는 메인 메모리 DBMS를 유지하는 것이 필요하다. 기존에 제시된 메인 메모리 색인으로는 T-tree 가 있는데, 이는 1차원 데이터를 위한 것이므로 이동체 데이터베이스 환경에 적합하지 못하다. 그리고, 디스크 기반의 다차원 색인으로는 R-tree 계열이 있는데, 이는 메인 메모리에서 효율적인 사용을 보장하지 못한다. 이 논문에서는 이동체 데이터베이스 환경에 적합한 메인 메모리 색인을 고려함에 있어서, 기존의 디스크 기반의 다차원 색인으로 가장 널리 알려진 R-tree 계열의 색인을 메인 메모리에 적재 후 메인 메모리 환경에서 성능에 영향을 주는 요소를 실험을 통하여 제시한다. 실험은 메인 메모리에서는 간단한 알고리즘을 사용하는 것이 성능에 좋고, 삽입 시에는 삽입할 노드를 찾기 위해서 비교하는 엔트리의 수가, 검색 시에는 노드간의 중첩으로 인하여 비교하는 노드의 수와 엔트리의 수가 성능에 영향을 주는 요소임을 보여준다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.30-36
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.

• Journal of Korea Multimedia Society
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• v.16 no.4
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• pp.483-492
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• 2013

SURF is an algorithm which extracts feature points and generates their descriptors from input images, and it is being used for many applications such as object recognition, tracking, and constructing panorama pictures. Although SURF is known to be robust to changes of scale, rotation, and view points, it is hard to implement it in real time due to its complex and repetitive computations. Using 3.3 GHz Pentium, in our experiment, it takes 240ms to extract feature points and create descriptors in a VGA image containing about 1,000 feature points, which means that software implementation cannot meet the real time requirement, especially in embedded systems. In this paper, we present a hardware architecture that can compute the SURF algorithm very fast while consuming minimum hardware resources. Two key concepts of our architecture are parallelism (for repetitive computations) and efficient line memory usage (obtained by analyzing memory access patterns). As a result of FPGA synthesis using Xilinx Virtex5LX330, it occupies 101,348 LUTs and 1,367 KB on-chip memory, giving performance of 30 frames per second at 100 MHz clock.

• Journal of Korea Game Society
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• v.12 no.5
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• pp.67-78
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• 2012

Summed area table allows filtering of arbitrary-width box regions for every pixel in constant time per pixel. This characteristic makes it beneficial in image processing applications where the sum or average of the surrounding pixel intensity is required. Although calculating the summed area table of an image data is primarily a memory bound job consisting of row or column-wise summation, previous works had to endure excessive access to the high latency global memory in order to exploit data parallelism. In this paper, we propose an efficient algorithm for generating the summed area table in the GPGPU environment where the input is decomposed into square sub-images with intermediate data that are propagated between them. By doing so, the global memory access is almost halved compared to the previous methods making an efficient use of the available memory bandwidth. The results show a substantial increase in performance.

• Journal of Korea Spatial Information System Society
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• v.8 no.2 s.17
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• pp.39-52
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• 2006

With the recent the use of spatio-temporal data mining which can extract various knowledge such as movement patterns of moving objects in history data of moving object gets increasing. However, the existing movement pattern extraction methods create lots of candidate movement patterns when the minimum support is low. Therefore, in this paper, we suggest the STMPE(Spatio-Temporal Movement Pattern Extraction) algorithm in order to efficiently extract movement patterns of moving objects from the large capacity of spatio-temporal data. The STMPE algorithm generalizes spatio-temporal and minimizes the use of memory. Because it produces and keeps short-term movement patterns, the frequency of database scan can be minimized. The STMPE algorithm shows more excellent performance than other movement pattern extraction algorithms with time information when the minimum support decreases, the number of moving objects increases, and the number of time division increases.

• Review of KIISC
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• v.2 no.2
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• pp.47-55
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• 1992

암호응용분야에 있어서의 이산대수 문제나 인수분해 문제는 방대한 양의 데이타를 다루는 문제로 많은 계산시간이 소요되므로 이들 문제들에 대한 고속 병렬처리는 매우 중요하다. 본 논문에서는 역행렬 문제나 이산대수 문제와 인수분해 문제의 중요한 과정인 선형시스템을 푸는데 효율적인 고속 병렬 알고리즘들을 소개한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.3
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• pp.427-435
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• 2023

Cardinality estimation is used in wide range of applications and a fundamental problem processing a large range of data. While the internet moves into the era of big data, the function addressing cardinality estimation use only on-chip cache memory. To use memory efficiently, there have been various methods proposed. However, because of the noises between estimator, which is data structure per flow, loss of accuracy occurs in these algorithms. In this paper, we focus on minimizing noises. We propose multiple data structure that each estimator has the number of estimated value as many as the number of structures and choose the minimum value, which is one with minimum noises, We discover that the proposed algorithm achieves better performance than the best existing work using the same tight memory, such as 1 bit per flow, through experiment.

• The Journal of the Korea Contents Association
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• v.13 no.9
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• pp.28-38
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• 2013

During the past decades, the B+-tree has been most widely used as an index file structure for disk-resident databases. For the disk based B+-tree, a node update can be cheaply performed just by modifying its associated disk page in place. However, in case that the B+-tree is stored on flash memory, the traditional algorithms of the B+-tree come to be useless due to the prohibitive cost of in-place updates on flash memory. For this reason, the earlier schemes for flash memory B+-trees usually take an approach that saves B+-tree changes from real-time updates into extra temporary storage. Although that approach can easily prevent frequent in-place updates in the B+-tree, it can suffer from a waste of storage space and prolonged search times. Particularly, it is not allowable to process range searches on the leaf node level. To resolve such problems, we devise a new scheme in which the leaf nodes and their parent node are stored together in a single flash block, called the p-node block.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.59-66
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• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.