• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2022.06a
• /
• pp.1311-1314
• /
• 2022

DNN을 사용하여 객체 인식 과정에서 객체를 잘 분류하기 위해서는 시각적 설명성이 요구된다. 시각적 설명성은 object class에 대한 예측을 pixel-wise attribution으로 표현해 예측 근거를 해석하기 위해 제안되었다, Scale-invariant한 특징을 제공하도록 설계된 pyramidal features 기반 backbone 구조는 object detection 및 classification 등에서 널리 쓰이고 있으며, 이러한 특징을 갖는 feature pyramid를 trainable attention mechanism에 적용하고자 할 때 계산량 및 메모리의 복잡도가 증가하는 문제가 있다. 본 논문에서는 일반적인 FPN에서 객체 인식 성능과 설명성을 높이기 위한 피라미드-주의집중 계층네트워크 (FPN-Attention Layered Network) 방식을 제안하고, 실험적으로 그 특성을 평가하고자 한다. 기존의 FPN만을 사용하였을 때 객체 인식 과정에서 설명성을 향상시키는 방식이 객체 인식에 미치는 정도를 정량적으로 평가하였다. 제안된 모델의 적용을 통해 낮은 computing 오버헤드 수준에서 multi-level feature를 고려한 시각적 설명성을 개선시켜, 결괴적으로 객체 인식 성능을 향상 시킬 수 있음을 실험적으로 확인할 수 있었다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2008.11a
• /
• pp.909-912
• /
• 2008

대용량 문서에 대한 키워드 검색을 위해 역파일(inverted-file) 색인 기법이 널리 쓰이고 있다. 역파일 색인 기법을 구현함에 있어 고려되어야 할 점은 키워드 검색 처리 시에 디스크 사용을 최소로 할 수 있는 방법이다. 크기가 작은 역파일이라면 디스크 I/O 사용도 작고 필요시 역파일을 메모리에 적재하여 둠으로써 디스크 사용을 크게 줄일 수 있다. 하지만, 웹 검색이나 규모가 큰 도서관 시스템에서와 같이 색인 데이터 크기가 매우 큰 경우 역파일을 읽는 디스크 비용이 급격히 증가할 수 있다. 본 논문에서는 매우 큰 크기의 역파일을 사용하는 검색 환경에서 디스크 사용을 최소로 할 수 있는 역파일 구조를 제안한다. 제안된 구조는 질의 처리 과정을 고려해 계층 구조로 설계되며 실제 상용 시스템에 적용되어 안정성 및 성능을 입증했다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2008.05a
• /
• pp.1147-1150
• /
• 2008

본 논문에서는 무선 센서 네트워크 상의 침입 탐지를 위한 동적인 방어 기법을 제안한다. 제안된 기법은 네트워크 상에 작은 수의 노드를 통하여 모니터링 작업을 수행하여 네트워크 상의 배터리 소모를 최소화함으로써 전체 네트워크의 라이프타임을 연장시킬 수 있도록 한다. 또한, 제안된 기법은 계층적 네트워크를 기반으로 한 간단한 구조를 갖고 있어, 센서 노드 내 배터리, 메모리, 컴퓨팅 파워 등의 제한된 자원에 효과적으로 대처할 수 있다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.36 no.3
• /
• pp.171-180
• /
• 2009

Slowly, but surely, we are seeing the emergence of a variety of embedded systems that are employing Storage Class RAM (SCRAM) such as FeRAM, MRAM and PRAM, SCRAM not only has DRAM-characteristic, that is, random byte-unit access capability, but also Disk-characteristic, that is, non-volatility. In this paper, we propose a new software architecture that allows SCRAM to be used both for main memory and for secondary storage simultaneously- The proposed software architecture has two core modules, one is a SCRAM driver and the other is a SCRAM manager. The SCRAM driver takes care of SCRAM directly and exports low level interfaces required for upper layer software modules including traditional file systems, buddy systems and our SCRAM manager. The SCRAM manager treats file objects and memory objects as a single object and deals with them in a unified way so that they can be interchanged without copy overheads. Experiments conducted on real embedded board with FeRAM have shown that the SCRAM driver indeed supports both the traditional F AT file system and buddy system seamlessly. The results also have revealed that the SCRAM manager makes effective use of both characteristics of SCRAM and performs an order of magnitude better than the traditional file system and buddy system.

• The Journal of the Korea Contents Association
• /
• v.18 no.3
• /
• pp.70-80
• /
• 2018

Due to the recent development of social media and mobile devices, graph data have been using in various fields. In addition, caching techniques for reducing I/O costs in the process of large capacity graph data have been studied. In this paper, we propose a multi-layer caching scheme considering the connectivity of the graph, which is the characteristics of the graph topology, and the history of the past subgraph usage. The proposed scheme divides a cache into Used Data Cache and Prefetched Cache. The Used Data Cache maintains data by weights according to the frequently used sub-graph patterns. The Prefetched Cache maintains the neighbor data of the recently used data that are not used. In order to extract the graph patterns, their past history information is used. Since the frequently used sub-graphs have high probabilities to be reused, they are cached. It uses a strategy to replace new data with less likely data to be used if the memory is full. Through the performance evaluation, we prove that the proposed caching scheme is superior to the existing cache management scheme.

• KSCE Journal of Civil and Environmental Engineering Research
• /
• v.29 no.2D
• /
• pp.311-318
• /
• 2009

Interactive terrain visualization is an important research area with applications in GIS, games, virtual reality, scientific visualization and flight simulators, besides having military use. This is a complex and challenging problem considering that some applications require precise visualizations of huge data sets at real-time rates. In general, the size of data sets makes rendering at real-time difficult since the terrain data cannot fit entirely in memory. In this paper, we suggest the effective Real-time LOD(level-of-detail) algorithm for displaying the huge terrain data and processing mass geometry. We used a hierarchy structure with $4{\times}4$ and $2{\times}2$ tiles for real-time rendering of mass volume DEM which acquired from Digital map, LiDAR, DTM and DSM. Moreover, texture mapping is performed to visualize realistically while displaying height data of normalized Giga Byte level with user oriented terrain information and creating hill shade map using height data to hierarchy tile structure of file type. Large volume of terrain data was transformed to LOD data for real time visualization. This paper show the new LOD algorithm for seamless visualization, high quality, minimize the data loss and maximize the frame speed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.4 s.334
• /
• pp.9-18
• /
• 2005

This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
• /
• v.29 no.1
• /
• pp.39-46
• /
• 2011

The present study introduces a comparison between 3D R-tree and octree which are noticeable candidates to index large point clouds gathered from a 3D terrestrial laser scanner. A query method, which is to find neighboring points within given distances, was devised for the comparison, and time lapses for the query along with memory usages were checked. From tests conducted on point clouds scanned from a building and a stone pagoda, it was shown that octree has the advantage of fast generation and query while 3D R-tree is more memory-efficient. Both index and leaf capacity were revealed to be ruling factors to get the best performance of 3D R-tree, while the number of level was of oetree.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.41 no.10
• /
• pp.805-812
• /
• 2013

The operational flight program(OFP) which has the functions of I/O processing with avionics, flight control logic calculation, fault diagnosis and redundancy mode is embedded in the flight control computer of Smart UAV. The OFP was developed in the environment of PowerPC 755 processor and VxWorks 5.5 real-time operating system. The OFP consists of memory access module, device I/O signal processing module and flight control logic module, and each module was designed to hierarchical structure. Memory access and signal processing modules were verified from bench test, and flight control logic module was verified from hardware-in-the-loop simulation(HILS) test, ground integration test, tethered test and flight test. This paper describes development environment, software structure, verification and management method of the OFP.

• Journal of KIISE:Databases
• /
• v.35 no.6
• /
• pp.469-480
• /
• 2008

A shared disk (SD) cluster couples multiple nodes for high performance transaction processing, and all the coupled nodes share a common database at the disk level. To reduce the number of disk accesses, each node caches database pages in its memory buffer. Since a particular page may be cached simultaneously in different nodes, cache consistency should be maintained to ensure that nodes can always access the most recent version of database pages. Most cache consistency schemes proposed in the SD cluster adopted LRU as a buffer replacement algorithm. In this paper, we first present four buffer replacement algorithms that consider the characteristics of the SD cluster. Then we compare the performance of the buffer replacement algorithms. We perform the experiments on a variety of cluster configurations and database workloads. The experiment results show that the proposed algorithms achieve performance improvement up to 5 times of LRU algorithm.