• Journal of Satellite, Information and Communications
• /
• v.1 no.2
• /
• pp.63-70
• /
• 2006

This paper presents the results of Ka band qualification model multiplexers for COMS Payload to be launched in 2008. These are the input and output multiplexers of the satellite transponder to use available frequency resources effectively and the diplexer of the satellite antenna to use the same reflector for both transmitting and receiving frequency bands, respectively. The input multiplexer with four frequency channels has four(4) independent channel filters which consist of an 8-pole elliptic band-pass filter for high frequency selectivity and a 2-pole equalizer for group delay equalization. For low insertion loss, mass and volume reduction, manifold type os employed for output multiplexer. E-plane T-junction is used for either splitting or combining a frequency band into two sub-bands. Asymmetric inductive irises are used to tune the receiving filter easily. The electrical performance and environmental test such as vibration test, mechanical shock test, thermal vacuum test and EMC test are performed and the results of all qualification model multiplexers are compliant to the requirement of each multiplexer. Followed by this qualification, the flight model equipment will be developed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.1B
• /
• pp.201-208
• /
• 2000

In the transmitter of optical communication systems, a time-division multiplexer combines several parallel data streams into a single data stream with a high bit rate. In this paper, we design a 4:1 (4-channels) time-division multiplexer using SiGe HBT with emitter size of 2x8um2. The operation speed is 100bps, the rise and fall times of 20-80% are 34ps and 34ps, respectively and the dissipation of power is 1.50W.

• Journal of Navigation and Port Research
• /
• v.29 no.1 s.97
• /
• pp.91-96
• /
• 2005

The National Marine Electronics Association(NMEA) is nonprofit-making cooperation composed with manufacturers, distributors, wholesalers and educational institutions. We use the basic port of equipment in order to process the signal from NMEA signal using equipment. When we don't have enough one, we use the multi-port for processing. However, we need to have module development simulation which could multiplex and provide NMEA related signal that we could solve the problems in multi-port application and exclusive equipment generation for a number of signal. For now, we don't have any case or product using NMEA multiplexer so that we import expensive foreign equipment or embody NMEA signal transmission program like software, using multi-port. These have problems since we have to pay lots ci money and build separate processing part for every application programs. Besides, every equipment generating NMEA signal are from different manufactures and have different platform so that it could cause double waste and loss of recourse. For making up for it, I suggest the NMEA multiplexer embodiment, which could independently move by reliable process and high performance single hardware module, improve the memory efficiency of module by designing the optimized Queue, and keep having reliability for realtime communication among the equipment such as main input sensor equipment Gyrocompass, Echo-sound, and GPS.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.7B
• /
• pp.996-1005
• /
• 2001

본 논문에서는 ASIC 벤더의 셀 라이브러리와 MUX-based FPGA에 있는 고정된 입력을 갖는 연결구조의 수를 최소화하는 하드웨어 할당 알고리듬을 제안한다. 제안된 할당 알고리듬은 연산자간을 연결하는 신호선이 반복적으로 이용되어 연결 신호선 수가 최소가 될 수 있도록 연산자를 할당한다. 연결 구조를 고려한 이분할 그래프에 가중치를 설정하고 변수와 레지스터간의 최대 가중치 매칭을 구함으로써 레지스터 할당을 수행한다. 또한 연결구조에 대한 멀티플렉서의 중복 입력을 제거하고 연산자에 연결된 멀티플렉서간의 입력을 교환하는 입력 정렬 과정으로 연결구조를 최소화한다. 벤치마크 실험을 통하여 제안된 알고리즘의 효용성을 보인다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2000.10c
• /
• pp.428-430
• /
• 2000

최근 고속 가입자망의 급속한 보급과 인터넷 정보가전 개발의 활성화는 홈네트워킹으로 불리우는 새로운 컴퓨팅 환경을 등장시켰다. 홈네트워킹 환경에서는 IPv4 주소공간의 부족과 내부 네트워크와 기존의 인터넷 사이에 연결성을 제공하기 위해서 풀어야 할 문제들이 있다. 또한, 정보가전에 내장되어 있는 웹서버를 관리.제어.확장하기 위한 기능성도 제공되어야 한다. 본 연구에서는 홈네트워킹 환경에서 발생하는 문제점들을 효과적으로 해결할 수 있는 웹서버 멀티플렉서 프레임워크를 설계하고 구현한다.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.12
• /
• pp.7309-7316
• /
• 2014

In this paper, a triple-band multiplexer using a microstrip transmission line was designed and fabricated to make use of a low power portable base station. This multiplexer was used in the triple-band including the cellular, WCDMA and LTE mobile frequency band, and designed to have an insertion loss of 0.8 dB, low SWR of 1.5 in the passband and a band rejection of 15 dB in the stopband. From the measured results obtained by a confidence test for the fabricated multiplexer samples, the maximum insertion loss and SWR of the fabricated multiplexer samples in all passbands of 824-894MHz, 1920-2170 MHz and 2500-2600 MHz were below 0.71 dB and 1.38, and the attenuations in the stopbands were better than 15 dB. Therefore, the triple-band multiplexer has good performance and satisfies the design specifications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.14 no.8
• /
• pp.839-844
• /
• 2003

For mass and volume reduction, input demultiplxer and output multiplexer of satellite transponder widely adopt dual-mode waveguide filters fer channel filters. Generally, channel filters of the input demultiplexer are doubly terminated and channel filters of manifold output multiplexer should be singly terminated fur correct operation. This paper gives a tuning method using short-ended dummy cavity for dual-mode cavity filters. Tuning is based on the match of the computed and measured phase response of reflection coefficient. This proposed method is applied to 4-pole dual-mode doubly terminated elliptic response filter and 6-pole dual-mode singly terminated elliptic response filter for demonstration of this new tuning method. It is shown that this method shows good agreement between the experimental and computed results.

• The Journal of the Convergence on Culture Technology
• /
• v.6 no.2
• /
• pp.515-520
• /
• 2020

CMOS used in digital circuit design technology has reached the limit of integration due to quantum tunneling. Quantum-dot cellular automata (QCA), which can replace this, has many advantages such as low power consumption and fast switching speed, so many digital circuits of CMOS have been proposed based on QCA. Among them, the multiplexer is a basic circuit used in various circuits such as D-flip-flops and resistors, and has been studied a lot. However, the existing multiplexer has a disadvantage that space efficiency is not good. Therefore, in this paper, we propose a new multilayered multiplexer using cell interaction and D-latch using it. The multiplexer and D-latch proposed in this paper have improved area, cell count, and delay time, and have excellent connectivity and scalability when designing large circuits. All proposed structures are simulated using QCADesigner to verify operation.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.4
• /
• pp.37-47
• /
• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1992.06a
• /
• pp.228-232
• /
• 1992