• KIPS Transactions on Computer and Communication Systems
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• v.9 no.2
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• pp.25-30
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• 2020

The thermal image system was widely used in the defence-related industry because of detect infrared light from the object without light. but, as the demand in the security system and automobile market increases, the civilian industry are expanding to the private sector. There are difficult to apply various requirement because of previous systems are based by FPGA, so it need new system that apply to various requirement. The proposed paper is thermal image processing system using common image processor. It has various requirement and scalable to support image input/output interface and device driver. If it is used to proposed system, it reduce development cost and period than previous system based FPGA. Because there has very high accessibility. In addition, it expect to have satisfaction of customer requirements, development cost, development period, release date of product.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.3
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• pp.331-335
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• 2008

In this paper, we parallelized a feature point extraction algorithm to reduce panorama image generation time in multi-core environment. While we compose a panorama image with several images, the step to extract feature points of each picture is needed to find overlapped region of pictures. To perform rapidly feature extraction stage which requires much calculation, we developed a parallel algorithm to extract feature points and examined the performance using CBE(Cell Broadband Engine) which is asymmetric multi-core architecture. As a result of the exam, the algorithm we proposed has a property of linear scalability-the performance is increased in proportion the number of processors utilized. In this paper, we will suggest how Image processing operation can make high performance result in multi-core environment.

• Journal of the Korea Society of Computer and Information
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• v.16 no.1
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• pp.1-9
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• 2011

Recently, as mobile multimedia devices are used more and more, the needs for high-performance and low-energy multimedia processors are increasing. Application-specific integrated circuits (ASIC) can meet the needed high performance for mobile multimedia, but they provide limited, if any, generality needed for various application requirements. DSP based systems can used for various types of applications due to their generality, but they require higher cost and energy consumption as well as less performance than ASICs. To solve this problem, this paper proposes a single instruction multiple data (SIMD) based many-core processor which supports high-performance and low-power image data processing while keeping generality. The proposed SIMD based many-core processor composed of 16 processing elements (PEs) exploits large data parallelism inherent in image data processing. Experimental results indicate that the proposed SIMD-based many-core processor higher performance (22 times better), energy efficiency (7 times better), and area efficiency (3 times better) than conversional commercial high-performance processors.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.11-21
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• 2011

This paper introduces an SIMD(Single Instruction Multiple Data) based parallel processor that efficiently processes massive data inherent in multimedia. In addition, this paper implements MMX(MultiMedia eXtension)-type instructions on the data parallel processor and evaluates and analyzes the performance of the MMX-type instructions. The reference data parallel processor consists of 16 processors each of which has a 32-bit datapath. Experimental results for a JPEG compression application with a 1280x1024 pixel image indicate that MMX-type instructions achieves a 50% performance improvement over the baseline instructions on the same data parallel architecture. In addition, MMX-type instructions achieves 100% and 51% improvements over the baseline instructions in energy efficiency and area efficiency, respectively. These results demonstrate that multimedia specific instructions including MMX-type have potentials for widely used many-core GPU(Graphics Processing Unit) and any types of parallel processors.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.339-349
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• 2017

This paper proposes a four-stage algorithm for detecting lanes on a driving car. In the first stage, it extracts region of interests in an image. In the second stage, it employs a median filter to remove noise. In the third stage, a binary algorithm is used to classify two classes of backgrond and foreground of an input image. Finally, an image erosion algorithm is utilized to obtain clear lanes by removing noises and edges remained after the binary process. However, the proposed lane detection algorithm requires high computational time. To address this issue, this paper presents a parallel implementation of a real-time line detection algorithm on a multi-core architecture. In addition, we implement and simulate 8 different processing element (PE) architectures to select an optimal PE architecture for the target application. Experimental results indicate that 40×40 PE architecture show the best performance, energy efficiency and area efficiency.