• Title/Summary/Keyword: 멀티코어

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Medical Image Classification and Retrieval Using Ensemble Combination of Visual Descriptors (시각 기술자들의 앙상블 결합을 이용한 의료 영상 분류와 검색)

  • Ki-Hee Park;Jeong-Hee Shim;Byoung-Chul Ko;Jae-Yeal Nam
    • Proceedings of the Korea Information Processing Society Conference
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    • 2008.11a
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    • pp.96-99
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    • 2008
  • 본 논문은 의료 영상을 효과적으로 분류하고 검색 하기 위한 새로운 알고리즘을 제안한다. 의료 영상 중 X-Ray 영상은 어두운 배경에 반해 밝은 전경을 갖고 있기 때문에, 전경의 두드러진 부분에서만 시각 기술자로 추출한다. 우선, 색 구조 기술자(H-CSD)에서 해리스 코너 검출기로 검출한 관심 포인트들에서 색상 특징을 추출하고, 경계선 히스토그램 기술자에서 영상의 전역 및 지역적 질감 특징을 추출한다. 추출된 특징 벡터는 멀티클래스 SVM 에 적용되어 각 영상을 위한 멤버십 스코어를 얻는다. 이후, H-CSD와 EHD 에 대한 SVM 의 멤버십 스코어를 앙상블 결합하여 하나의 특징 벡터로 생성하고, K-nearest Neighborhood 방법을 이용하여 상위-K 개의 영상을 검색을 하도록 하였다. imageCLEFmed2007 을 이용한 실험 결과에서 다른 전역적 속성 또는 분류 기반 검색 방법에 비교하여 보다 개선된 검색 성능을 나타냄을 확인하였다.

Implementation of an Optimal SIMD-based Many-core Processor for Sound Synthesis of Guitar (기타 음 합성을 위한 최적의 SIMD기반 매니코어 프로세서 구현)

  • Choi, Ji-Won;Kang, Myeong-Su;Kim, Jong-Myon
    • Journal of the Korea Society of Computer and Information
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    • v.17 no.1
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    • pp.1-10
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    • 2012
  • Improving operating frequency of processors is no longer today's issues; a multiprocessor technique which integrates many processors has received increasing attention. Currently, high-performance processors that integrate 64 or 128 cores are developing for large data processing over 2, 4, or 8 processor cores. This paper proposes an optimal many-core processor for synthesizing guitar sounds. Unlike the previous research in which a processing element (PE) was assigned to support one of guitar strings, this paper evaluates the impacts of mapping different numbers of PEs to one guitar string in terms of performance and both area and energy efficiencies using architectural and workload simulations. Experimental results show that the maximum area energy efficiencies were achieved at PEs=24 and 96, respectively, for synthesizing guitar sounds with sampling rate of 44.1kHz and 16-bit quantization. The synthesized sounds were very similar to original guitar sounds in their spectra. In addition, the proposed many-core processor was 1,235 and 22 times better than TI TMS320C6416 in area and energy efficiencies, respectively.

Development of Multi-Touch/Context-Aware Convergence Digital Signage System based on Android OS Platform (안드로이드 플랫폼 기반 멀티 터치/상황인지형 융복합 디지털 사이니지 시스템 개발)

  • Nahm, Eui-Seok
    • Journal of Digital Convergence
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    • v.13 no.8
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    • pp.245-251
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    • 2015
  • If a digital signage system is operated in PC mounted in the Window OS then the implementing price is very high. For resolving this problem, we used the Smartphone mounted in ARM Cortex family of multi-core processor-based mobile platform. We developed a low-power low-cost digital signage system and a remote convergence content management program based on web server. This convergence system manages advertising content to a remote control device anywhere using remote control technology. This system is one integrated system with display and is a low-power consumed and is developed in very efficient hardware interface. And condition sensors(intensity of illumination, temperature, weather, GPS etc) is equipped in the developed system. Automatic contents builder and Context-aware SMIL module is also implemented in the convergence system. We achieved over 50% power savings comparing with conventional Window OS system and 16 points multi-touch in our system.

Convergence of Broadcasting and Communication in Home Network using E-PON based Home Gateway (EPON 기반 홈게이트웨이를 이용한 댁내 망에서의 방송통신 융합 서비스)

  • Park Wanki;Kim Daeyoung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.6 s.336
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    • pp.9-16
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    • 2005
  • In this paper, we focus on supporting the convergence of broadcasting and communication in home network systems with E-PON based home gateway. We propose a new architecture to provide broadcasting and data services in integrated home network using overlay transport mechanism in access network and If multicast techniques of IGMP and IGMP snooping in home network. We also detail a set of mechanisms and procedures for home broadcasting service through the home gateway system. Our new scheme is composed of three parts: a) an overlay transmission model of video broadcasting signals (satellite and/or cable TV) and Internet data, b) to select a specific video broadcasting channel and to make of the selected video broadcasting stream into IP multicast packets in tuner/conversion module using multiple tuner system and c) to transfer the converted If multicast packets to L2 switch of home gateway's core module and to send them out to target port(s) by L2 multicast using IGMP snooping.

Performance analysis of private multimedia caching network based on wireless local area network (WLAN 기반 개인형 멀티미디어 캐싱 네트워크 성능 분석)

  • Ban, Tae-Won;Kim, Seong Hwan;Ryu, Jongyeol;Lee, Woongsup
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.8
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    • pp.1486-1491
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    • 2017
  • In this paper, we propose a private multimedia caching scheme based on wireless local area network (WLAN) to improve the quality of service for high capacity and high quality multimedia streaming services which are recently increasing and to reduce the traffic load of core networks. The proposed caching scheme stores multimedia in the storage device mounted on WLAN APs and provides streaming services on its own without Internet connection in accordance with the request from clients. We have implemented a test network based on real commercial networks and measured the performance of the proposed caching scheme in terms of frames per second (FPS) and buffering time. According to the performance measurement results, the proposed caching scheme can reduce the average buffering time by 73.3% compared to the conventional streaming scheme. In addition, the proposed caching scheme can also improve the average FPS by 71.3% compared to the conventional streaming scheme.

2-Layered Group Key Management Structure and Protocols using Multi-Core Based Tree (다중 코어 기반 트리를 이용한 2계층 그룹키 관리 구조 및 프로토콜)

  • Cho, Tac-Nam;Kim, Sang-Hee;Eun, Sang-A;Lee, Sang-Ho;Chae, Ki-Joon;Park, Won-Joo;Nah, Jae-Hoon
    • Journal of KIISE:Information Networking
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    • v.29 no.5
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    • pp.583-594
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    • 2002
  • Assuring the security of group communications such as tole-conference and software distribution requires a common group key be shared among the legal members in a secure manner. Especially for large groups with frequent membership change, efficient rekey mechanism is essential for scalability. One of the most popular ways to provide sealable rekey is to partition the group into several subgroups. In this paper, we propose a two-layered key management scheme which combines DEP and CBT, a protocol in which subgroup manager cannot access the multicast data and another that has a multi-core, respectively. We also select sub-group key management protocols suitable for our structure and design new rekey protocols to exclude the subgroup managers from the multicast data. Compared to previous protocols based on CBT, our scheme provides forward secrecy, backward secrecy and scalability. This would reduce the number of encryption and decryption for a rekey message and would improve the efficiency number of rekey messages and the amount of information related to group members that group managers must maintain compared to DEP.

Performance Evaluation of Big Stream based High Speed Data Storage (빅 스트림 기반 초고속 데이터 스토리지 성능 평가)

  • Song, Min-Gyu;Kang, Yong-Woo;Kim, Hyo-Ryoung
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.5
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    • pp.817-828
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    • 2017
  • It is very hard to find the system which processes single 10Gbps stream, and the related application is also rare. But in the field of science such as physics and astronomy, these high speed systems have been widely used and now more upgraded performance is expected. For this reason, high speed network based storage which captures and records 10Gbps level of packets was developed for the support of small astronomical company in KASI. But for the use of the system in research, system performance should be not only evaluated but also optimized. In this paper, we first implement system environment for the performance evaluation and discuss the experiment procedure and solution to acquire numerical results.

A Task Scheduling Strategy in a Multi-core Processor for Visual Object Tracking Systems (시각물체 추적 시스템을 위한 멀티코어 프로세서 기반 태스크 스케줄링 방법)

  • Lee, Minchae;Jang, Chulhoon;Sunwoo, Myoungho
    • Transactions of the Korean Society of Automotive Engineers
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    • v.24 no.2
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    • pp.127-136
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    • 2016
  • The camera based object detection systems should satisfy the recognition performance as well as real-time constraints. Particularly, in safety-critical systems such as Autonomous Emergency Braking (AEB), the real-time constraints significantly affects the system performance. Recently, multi-core processors and system-on-chip technologies are widely used to accelerate the object detection algorithm by distributing computational loads. However, due to the advanced hardware, the complexity of system architecture is increased even though additional hardwares improve the real-time performance. The increased complexity also cause difficulty in migration of existing algorithms and development of new algorithms. In this paper, to improve real-time performance and design complexity, a task scheduling strategy is proposed for visual object tracking systems. The real-time performance of the vision algorithm is increased by applying pipelining to task scheduling in a multi-core processor. Finally, the proposed task scheduling algorithm is applied to crosswalk detection and tracking system to prove the effectiveness of the proposed strategy.

A Performance Study of Multi-core Out-of-Order Superscalar Processor Architecture (멀티코어 비순차 수퍼스칼라 프로세서의 성능 연구)

  • Lee, Jong-Bok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.10
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    • pp.1502-1507
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    • 2012
  • In order to overcome the hardware complexity and power consumption problems, recently the multi-core architecture has been prevalent. For hardware simplicity, usually RISC processor is adopted as the unit core processor. However, if the performance of unit core processor is enhanced, the overall performance of the multi-core processor architecture can be further increased. In this paper, out-of-order superscalar processor is utilized for the multi-core processor architecture. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the out-of-order superscalar cores between 2 and 16 extensively. As a result, the 16-core out-of-order superscalar processor for the window size of 16 resulted in 17.4 times speed up over the single-core out-of-order superscalar processor, and 50 times speed up over the single core RISC processor. When compared for the same number of cores on the average, the multi-core out-of-order superscalar processor performance achieved 3.2 times speed up over the multi-core RISC processor and 1.6 times speed up over the multi-core in-order superscalar processor.

Development of Scalable Video Encoder S/W using layer based multi-processing (레이어 단위 멀티 프로세싱을 이용한 스케일러블 비디오 인코더 S/W 개발)

  • Yi, Joo-Young;Kim, Jewoo;Kim, Yong-Hwan;Choi, Byeong Ho
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2011.07a
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    • pp.598-601
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    • 2011
  • 스케일러블 비디오 코딩은 레이어간 예측 기능을 이용하여 시뮬케스트 코딩에 비해 코딩 효율을 높인다. 하지만 스케일러블 비디오 코딩의 레이어간 예측으로는, 인트라 픽셀(inta pixel). 모션 정보(motion vector information), 레지듀얼(residual)등의 예측이 수행되는데, 이는 많은 계산 시간을 소요하게 되며, 시뮬케스트에 비해 코딩 시간이 증가하게 된다. 특히 인코더의 경우, 가장 최적의 모드를 선택하기 위하여, 기존 H.264 AVC에서 사용하는 예측을 수행한 뒤, 부가적으로 스케일러블 비디오 코딩의 레이어간 예측을 수행하기 때문에, 하나의 영상이 많은 레이어를 포함할수록 인코딩에 의한 계산부하가 매우 증가하게 된다. 본 논문에서는 이를 해결하기 위해, 멀티 코어 이용하여 레이어별로 병렬처리가 가능하도록 하는 스케일러블 비디오 인코더의 구조를 제안한다. 이로써 하나의 영상이 포함하는 레이어의 수가 증가함에 따라 발생하는 인코딩 계산 부하를 줄이도록 하였다. 그리하여 본 논문에서 제안하는 구조를 적용하였을 때, 2개의 공간영역으로의 스케일러빌리티를 가지는 영상들에 대해서는 평균 24.8%의 속도가 향상되었고, 1개의 공간영역과 1개의 화질 영역으로의 스케일러빌리티를 가지는 영상들에 대해서는 평균 82%의 속도 향상을 보였다.

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