• KIPS Transactions on Computer and Communication Systems
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• v.12 no.7
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• pp.209-216
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• 2023

Modern HPC systems are equipped with many-core CPUs with dozens of cores. When performing parallel I/O in such a system, there is a limit to scalability due to the problem of the LRU lock management policy of the Linux system. The study proposes an improved FinerLRU to solve this problem. Our new FinerLRU improves the parallel write performance of file systems using the buffer cache through granular lock management by increasing the number of LRU locks upto the maximum number of cores. The proposed method was implemented in Linux 5.18.11, and the performance was measured on two types of CPUs, Intel Icelake Xeon and Intel Knights landing, with different characteristics, and it was found that a performance improvement of about two times can be obtained in both types of systems.

• Journal of KIISE
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• v.44 no.9
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• pp.878-886
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• 2017

This paper discusses performance bottlenecks that may occur when executing high-performance computing MPI applications in the Intel's next generation many-core processor called Knights Landing(KNL), as well as effective resource allocation techniques to solve this problem. KNL is composed of a host processor to enable self-booting in addition to an existing accelerator consisting of a many-core processor, and it was released with a new type of on-package memory with improved bandwidth on top of existing DDR4 based memory. We empirically verified an improvement of the execution performance of multiple MPI applications and the overall system utilization ratio by studying a resource allocation method optimized for such new many-core processor architectures.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.35 no.10
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• pp.32-38
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• 2017

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.32 no.5
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• pp.34-41
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• 2014

• Journal of the Korea Society of Computer and Information
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• v.17 no.1
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• pp.1-10
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• 2012

Improving operating frequency of processors is no longer today's issues; a multiprocessor technique which integrates many processors has received increasing attention. Currently, high-performance processors that integrate 64 or 128 cores are developing for large data processing over 2, 4, or 8 processor cores. This paper proposes an optimal many-core processor for synthesizing guitar sounds. Unlike the previous research in which a processing element (PE) was assigned to support one of guitar strings, this paper evaluates the impacts of mapping different numbers of PEs to one guitar string in terms of performance and both area and energy efficiencies using architectural and workload simulations. Experimental results show that the maximum area energy efficiencies were achieved at PEs=24 and 96, respectively, for synthesizing guitar sounds with sampling rate of 44.1kHz and 16-bit quantization. The synthesized sounds were very similar to original guitar sounds in their spectra. In addition, the proposed many-core processor was 1,235 and 22 times better than TI TMS320C6416 in area and energy efficiencies, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.866-869
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• 2015

With the advance in semiconductor technology, the number of elements that can be integrated in system-on-chip(SoC) increases exponentially, and thus voltage scaling is indispensable to enhance energy efficiency. Near-threshold voltage computing(NTC) improves the energy efficiency by an order of degree, hence it is able to overcome the limitation of conventional super-threshold voltage computing(STC). Although NTC-based low performance manycore system can be used to maximize energy efficiency, it demands more number of cores to sustain the performance, which results in considerable increase of area. In this paper, we analyze NTC manycore architecture considering the trade-offs between performance, power, and area. Therefore, we propose an algorithmic methodology that can optimize power consumption and area while satisfying the required performance by determining the constrained number of cores and size of caches and clusters in NTC environment. Experimental results show that proposed NTC architecture can reduce power consumption by approximately 16.5 % while maintaining the performance of STC core under area constraint.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.35 no.10
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• pp.8-17
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• 2017

• Korea Information Processing Society Review
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• v.25 no.1
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• pp.78-88
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• 2018

• Electronics and Telecommunications Trends
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• v.27 no.6
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• pp.124-133
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• 2012

최근 산업의 발전으로 대규모 문제 해결의 요구가 커지고 사용자가 원하는 서비스를 신속하게 받고자 고성능 컴퓨팅에 대한 요구가 계속해서 증가하고 있다. 이에 따라 멀티코어 및 매니코어와 이종 하드웨어의 혼용 등으로 지속해서 발전하는 새로운 고성능 컴퓨팅을 위한 시스템은 컴퓨팅 패러다임을 바꿀 시스템 소프트웨어의 혁신 요소로 등장하였다. 하드웨어를 활용하여 시스템의 성능을 높이기 위해서는 컴퓨팅 요소 간의 통신을 최소화하여 전력 소모를 줄이고, 메모리 계층 구조 및 지역성을 고려하여 성능을 높이는 것이 필요하다. 특히, 응용의 실행 시에 시스템 자원을 최고로 활용할 수 있게 하여 성능을 높이는 런타임 시스템은 하드웨어 및 운영체제를 변경하지 않고 시스템 자원을 최대한 활용하여 성능 최적화를 이룰 수 있는 기술이다. 따라서 본고에서는 런타임 시스템의 기능과 기술 방향을 파악하여 차세대 런타임 시스템에 필요한 기술 및 연구 분야를 전망하고자 한다.

• The KIPS Transactions:PartA
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• v.19A no.3
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• pp.121-128
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• 2012

This paper explores the optimal processing element (PE) configuration for ultrasonic image processing at different resolutions ($256{\times}256$, $768{\times}1,024$, and $1,024{\times}1,280$). To determine the optimal PE configuration, this paper evaluates the impacts of a data-per-processing element (DPE) ratio that is defined as the amount of image data directly mapped to each PE on system performance and both energy and area efficiencies using architectural and workload simulations. This paper illustrates the correlation between DPE ratio and PE architecture for a target implementation in 130nm technology. To identify the most efficient PE structure, seven different PE configurations were simulated for ultrasonic image processing. Experimental results indicate that the highest energy efficiencies were achieved at PEs=1,024, 4,096, and 16,384 for ultrasonic images at $256{\times}256$, $768{\times}1,024$, $1,024{\times}1,280$ resolutions, respectively. Furthermore, the maximum area efficiencies were yielded at PEs=256 ($256{\times}256$ image) and 4,096 ($768{\times}1,024$ and $1,024{\times}1,280$ images), respectively.