• Journal of the Korean Institute of Landscape Architecture
• /
• v.35 no.4
• /
• pp.90-104
• /
• 2007

Landmarks like high-rise building are one of the important elements for the enhancement of city identity and provides the hierarchy of city streets, playing a central and symbolic role in cities. Research on physical attribute of landmarks, such as height, distance, location and shape, which are suitable for a city scale, can help a city create a distinct image and maintain comprehensible structure. To achieve this purpose, it is necessary to understand the spatial and cognitive characteristics of a landmark for the establishment and management of it. The results of this study can be summarized as follows: 1. The level of representativeness of a landmark increases in proportion to the degree of cognitive intensity on it. The relation between representativeness and cognitive intensity can be explained as the log-function as follows: Log(the number of people who respond "It has representativeness")=$-1.2579+1.5908{\times}$(cognitive intensity); 2. There are a few differences based on the attributes of respondents: while gender has no distinct influence, residential period and age show statistically meaningful influence on cognitive intensity of a vertical landmark Cognitive intensity of an individual landmarks especially, differs according to the class of main users. Because of frequent changes in occupation or employment, respondents consider the distance from a residential area more important than the distance from a working area in evaluating cognitive intensity of landmarks; 3. landmark can be classified into two kinds: a district landmark and an urban landmark A district landmark is closely connected with physical attributes of the landmark itself, such as distance, size and height. An urban landmark is mainly related to cognitive attributes such as the image and identity of a city as a whole. As a result, the landmark analysis data in this research provides spatial order and identity in a city. It is difficult to establish and reinforce the image of a city as a single element ike a landmark. However, withy steady follow-up research, this study could be seen as a systematic and logical model to improve urban landscape and image.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.6
• /
• pp.306-313
• /
• 2005

Conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a simple mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the Simplescalar 3.0/PISA tool set and the SPECINTgS benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14$\%$ and 9.21$\%$, respectively and the average IPC by 8.75$\%$ and 18.08$\%$, respectively over the original predictor.

• Journal of KIISE:Software and Applications
• /
• v.32 no.10
• /
• pp.1003-1012
• /
• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

• Journal of KIISE:Computer Systems and Theory
• /
• v.26 no.9
• /
• pp.1177-1184
• /
• 1999

본 논문에서는 스캔플립프롭 선택 시간이 짧고 높은 고장 검출률(fault coverage)을 얻을 수 있는 새로운 부분스캔 설계 기술을 제안한다. 순차회로에서 테스트패턴 생성을 용이하게 하기 위하여 완전스캔 및 부분스캔 설계 기술이 널리 이용되고 있다. 스캔 설계로 인한 추가영역을 최소화 하고 최대의 고장 검출률을 목표로 하는 부분스캔 기술은 크게 구조분석과 테스트 가능도(testability)에 의한 설계 기술로 나누어 볼 수 있다. 구조분석에 의한 부분스캔은 짧은 시간에 스캔플립프롭을 선택할 수 있지만 고장 검출률은 낮다. 반면 테스트 가능도에 의한 부분스캔은 구조분석에 의한 부분스캔보다 스캔플립프롭의 선택 시간이 많이 걸리는 단점이 있지만 높은 고장 검출률을 나타낸다. 본 논문에서는 구조분석에 의한 부분스캔과 테스트 가능도에 의한 부분스캔 설계 기술의 장단점을 비교.분석하여 통합함으로써 스캔플립프롭 선택 시간을 단축하고 고장 검출률을 높일 수 있는 새로운 부분스캔 설계 기술을 제안한다. 실험결과 대부분의 ISCAS89 벤치마크 회로에서 스캔플립프롭 선택 시간은 현격히 감소하였고 비교적 높은 고장 검출률을 나타내었다.Abstract This paper provides a new partial scan design technique which not only reduces the time for selecting scan flip-flops but also improves fault coverage. To simplify the problem of the test pattern generation in the sequential circuits, full scan and partial scan design techniques have been widely adopted. The partial scan techniques which aim at minimizing the area overhead while maximizing the fault coverage, can be classified into the techniques based on structural analysis and testabilities. In case of the partial scan by structural analysis, it does not take much time to select scan flip-flops, but fault coverage is low. On the other hand, although the partial scan by testabilities generally results in high fault coverage, it requires more time to select scan flip-flops than the former method. In this paper, we analyzed and unified the strengths of the techniques by structural analysis and by testabilities. The new partial scan design technique not only reduces the time for selecting scan flip-flops but also improves fault coverage. Test results demonstrate the remarkable reduction of the time to select the scan flip-flops and high fault coverage in most ISCAS89 benchmark circuits.

• Journal of KIISE:Computing Practices and Letters
• /
• v.11 no.1
• /
• pp.15-25
• /
• 2005

Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.8
• /
• pp.719-729
• /
• 2000

Prefetching aims at reducing memory latency by fetching, in advance, data that are likely to be requested by the processor in a near future. The effectiveness of prefetching is determined by how accurate the prediction on the needed instructions and data is. Most previous studies on prefetching were limited to proposing a particular prefetch scheme and its performance evaluation, paying little attention to theoretical aspects of prefetching. This paper focuses on the theoretical aspects of instruction prefetching. For this purpose, we propose a clairvoyant prefetch model that makes use of perfect history information. Based on this theoretical model, we analyzed upper limits on the prefetch prediction accuracies of the SPEC benchmarks. The results show that the prefetch prediction accuracy is very high when there is no cache. However, as the size of the instruction cache increases, the prefetch prediction accuracy drops drastically. For example, in the case of the spice benchmark, the prefetch prediction accuracy drops from 53% to 39% when the cache size increases from 2Kbyte to 16Kbyte (assuming 16byte block size). These results indicate that as the cache size increases, most localities are captured by the cache and that instruction prefetching based on the information extracted from the references that missed in the cache suffers from prediction inaccuracies

• Proceedings of the Korea Information Processing Society Conference
• /
• 2001.04b
• /
• pp.743-746
• /
• 2001

자바는 객체지향 언어이고, 한번 작성된 프로그램은 자바 가상 기계가 있는 모든 곳에서 수정없이 실행될 수 있기 때문에 소프트웨어의 개발과 유지 보수에 많은 장점을 가진 언어이다. 이러한 특징으로 인하여 개발되는 제품들이 자바로 구현되는 경우가 많다. 그러나 아직 대다수 소프트웨어 개발자들은 주로 C 언어나 C++ 언어를 사용하고 있으며, 최근에는 C#이라는 언어를 사용하고 있다. 자바가 플랫폼에 독립적인 장점은 가지고 있지만, 다수의 개발자 및 사용자가 마이크로소프트 윈도우 운영체제를 사용하고 있다는 것을 감안한다면 그리 탁월한 장점만은 될 수 없다. 또한, 최근의 개발동향이 COM(Component Object Model)을 지향하고 있고, 이는 더 이상 개발자들에게 프로그래밍 언어에 구애를 받지 않고 오직 개발 제품에 대한 집중력을 가질 수 있는 환경을 제공할 수 있다면, 그 개발 효율에 있어서 상당한 이점을 가질 수 있다는 의미이다. 따라서, COL(Component Object Language)을 기반으로 하고 있는 C# (C sharp)언어를 사용하여 개발을 함에 있어서 자바의 언어를 C# 언어로 변환할 수 있다면, 신생 언어인 C#에 있어서 기존 자바로 되어 있는 유용한 개발 제품들을 보다 효율적으로 이용할 수 있을 것이다. 본 논문에서는 두 언어(자바, C#)를 하나로 잇는 교량(bridge)역할을 할 수 있도록 자바의 중간 언어인 Bytecode를 C#의 중간 언어인 MSIL(Microsoft Intermediate Language)로 바꿀 수 있는 중간 언어 번역기를 설계하고 구현하였다. 이를 위한 방법으로는 먼저, 자바 Bytecode 와 MSIL 의 어셈블리 형태에서의 명령어 매칭과정을 매핑 테이블을 이용하여 처리하였고, MSIL 에서 자바 Bytecode 의 함수와 같은 기능을 하는 메소드의 변환을 위하여 마크로 변환기법을 이용하여 해결하였다.I/O ratio 2.5). BTEX의 상대적 함량도 실내가 실외보다 높아 실내에도 발생원이 있음을 암시하고 있다. 자료 분석결과 유치원 실내의 벤젠은 실외로부터 유입되고 있었고, 톨루엔, 에틸벤젠, 크실렌은 실외뿐 아니라 실내에서도 발생하고 있었다. 정량한 8개 화합물 각각과 총 휘발성 유기화합물의 스피어만 상관계수는 벤젠을 제외하고는 모두 유의하였다. 이중 톨루엔과 크실렌은 총 휘발성 유기화합물과 좋은 상관성 (톨루엔 0.76, 크실렌, 0.87)을 나타내었다. 이 연구는 톨루엔과 크실렌이 총 휘발성 유기화합물의 좋은 지표를 사용될 있고, 톨루엔, 에틸벤젠, 크실렌 등 많은 휘발성 유기화합물의 발생원은 실외뿐 아니라 실내에도 있음을 나타내고 있다.>10)의 $[^{18}F]F_2$를 얻었다. 결론: $^{18}O(p,n)^{18}F$ 핵반응을 이용하여 친전자성 방사성동위원소 $[^{18}F]F_2$를 생산하였다. 표적 챔버는 알루미늄으로 제작하였으며 본 연구에서 연구된 $[^{18}F]F_2$가스는 친핵성 치환반응으로 방사성동위원소를 도입하기 어려운 다양한 방사성의 약품개발에 유용하게 이용될 수 있을 것이다.었으나 움직임 보정 후 영상을 이용하여 비교한 경우, 결합능 변화가 선조체 영역에서 국한되어 나타나며 그 유의성이 움직임 보정 전에 비하여 낮음을 알 수 있었다. 결론: 뇌활성화 과제 수행시에 동반되는 피험자의 머리 움직임에 의하여 도파민 유리가 과대평가되었으며 이는 이 연구에서 제안한 영상정합을 이용한 움직임 보정기법에 의해서 개선되었다. 답이 없는 문제, 문제 만들기, 일반화가 가능한 문제 등으로 보고, 수학적 창의성 중 특히 확산적 사고에 초점을 맞추어 개방형 문제가 확산적 사고의 요소인 유창성, 독창성, 유연성 등에 각각 어떤 영향을 미치는지 20주의 프로그램을 개발, 진행하여 그 효과를

• The KIPS Transactions:PartB
• /
• v.10B no.6
• /
• pp.599-610
• /
• 2003

The Web plays an important role as information source and most Web applications are document-centric. A document implies an intention of its own designer, which can be utilized actively in automation of business processes. Through an understanding of an intrinsic nature of a document function, we can see a document as an executable computer program in a special case. For this approach, we propose an active document model that is composed of form, knowledge base, rules, and queries. For reusability and interoperability of a document, each component of the proposed model is uniformly represented in XML. The proposed active document not only plays a passive role in providing user interfaces, but also is a document that a machine can infer and process with reading a procedure of document processing and business rules intended by document designers. Through this approach, document can interact with machines and can cooperate with other applications. For applicability of our active document, we show a case study for the processing of purchase orders in a B2B e-Commerce system. This paper is expected to provide the framework of accelerating the development of intelligent applications through our approach regards form document as a computer program. In short, the proposed active document contains knowledge representation and processing method, consequently our document will play an important role in providing a concept of document of pursuing in Semantic Web.

• The KIPS Transactions:PartA
• /
• v.17A no.1
• /
• pp.9-18
• /
• 2010

Races that occur in shared-memory parallel programs such as OpenMP programs must be detected for debugging because of causing unintended non-deterministic results. Previous works which verify the existence of these races on-the-fly are limited to the programs without internal non-determinism. But in the programs with internal non-determinism, such works need at least N! execution instances for each critical section to verify the existence of races, where N is the degree of maximum parallelism. This paper presents a preprocessor that statically analyzes the locations of non-deterministic accesses using program slicing and can detect apparent races as well as potential races through single execution using the analyzed information. The suggested tool can deterministically monitor non-deterministic accesses to occur in OpenMP programs so that this tool can verify the existence of races even if it is used any race detection protocol which can apply to programs with critical section. To prove empirically this tool, we have experimented using a set of benchmark programs such as synthetic programs that involve non-deterministic accesses, OpenMP Microbenchmark, NAS Parallel Benchmark, and OpenMP application programs.

• Journal of KIISE:Computer Systems and Theory
• /
• v.36 no.6
• /
• pp.476-487
• /
• 2009

The virtual memory system in 4.4 BSD operating systems exploits a clustering scheme to reduce disk I/Os in paging out (or flushing) modified pages that are intended to be replaced in order to make free rooms in memory. Upon the page out of a victim page, the scheme stores a cluster (or group) of modified pages contiguous with the victim in the virtual address space to swap disk at a single disk write. However, it fails to find large clusters of contiguous pages if applications change pages not adjacent with each other in the virtual address space. To address the problem, we propose a new clustering scheme called Multiple-Object Clustering (MOC), which together stores multiple clusters in the virtual address space at a single disk write instead of paging out the clusters to swap space at separate disk I/Os. This multiple-cluster transfer allows the virtual memory system to significantly decrease disk writes, thus improving the page-out performance. Our experiments in the FreeBSD 6.2 show that MOC improves the execution times of realistic benchmarks such as NS2, Scimark2 SOR, and nbench LU over the traditional clustering scheme ranging from 9 to 45%.