• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2007.04a
• /
• pp.49-65
• /
• 2007

• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.3
• /
• pp.55-62
• /
• 2001

With a spread of BGA, CSP and fine pitch devices, the need of flatter surface finish in bare board is becoming more critical in solderability. The electroless Ni/Au plating has a solution of these needs and also has being spread to apply to surface finish for bare board in many electronic goods. But, the electroless Ni/Au plating had several issues such as Ni oxidation and phosphorous contents. Before this study, we studied on the effect of BGA solderability in electroless Ni/Au plating and chose some major factors such as the oxidation property of NiP plating and warpage of board. Firstly, we made test board with various plating conditions and improved the plating property through the improvement of NiP oxidation reducing P content. Also, we minimized the warpage of board with the improvement of inner layer structure and the analysis of warpage. For the evaluation of solderability, we analyzed the warpage of board and the plating property after mounting BGA on the board with optimizing conditions. The solder joint of BGA is investigated by SEM(Scanning Electronic Microscope) and OM(Optical Microscope). The composition of joint is used by EDS(Energy Dispersive Spectroscopy). We analyzed the fracture strength and mode by ball shear teser.

• Journal of the Microelectronics and Packaging Society
• /
• v.9 no.2
• /
• pp.1-9
• /
• 2002

The intermetallic formation between Sn-Ag-(Cu) solders and metal pads in a real BGA package was characterized using SEM, EDS, and XRD. The intermetallic phase formed in the interface between Sn-Ag-Cu and Au/Ni/Cu pad is likely to be ternary compound of $(Cu,Ni)_6Sn_5$ from EDS analysis High concentration of Cu was observed in the solder/Ni interface. XRD analysis confirmed that $\eta -Cu_6 Sn_5$ type was intermetallic phase formed in the interface between Cu containing solders and Ni substrates and $Ni_3$Sn_4$ intermetallic was formed in the Sn-Ag solder/Ni interface. The thickness of intermetallic phase increased with the reflow times and Cu concentration in solder.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.3
• /
• pp.31-36
• /
• 2012

In this study, the complex vibration reliability of Sn-3.5Ag and Sn-0.7Cu having a high melting temperature was investigated. For manufacturing of BGA test samples, Sn-3.5Ag and Sn-0.7Cu balls were joined on BGA chips finished by ENIG and the chips were mounted on PCB finished OSP by using reflow process. For measuring of resistance change during complex vibration test, daisy chain was formed in the test board. From the results of resistance change and shear strength change, the reliability of two solder balls was compared and evaluated. During complex vibration for 120 hours, Sn-0.7Cu solder was more stable than Sn-3.5Ag solder in complex vibration test.

• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.4
• /
• pp.71-77
• /
• 2007

In this study, the mechanical and electrical properties of three different ball grid array (BGA) solder joints, consisting of Sn-37Pb, Sn-3.5Ag and Sn-3.5Ag-0.75Cu (all wt.%), with organic solderability preservative (OSP)-finished Cu pads were investigated as a function of reflow number. Based on scanning electron microscopy (SEM) analysis results, a continuous $Cu_6Sn5$, intermetallic compound (IMC) layer was formed at the solder/substrate interface, which grew with increasing reflow number. The ball shear testing results showed that the shear force peaked after 3 reflows (in case of Sn-Ag solder, 4 reflows), and then decreased with increasing reflow number. The electrical property of the joint gradually decreased with increasing reflow number.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2000.04a
• /
• pp.80-80
• /
• 2000

• Journal of the Microelectronics and Packaging Society
• /
• v.9 no.2
• /
• pp.39-43
• /
• 2002

The eutectic solder Sn-37Pb and the lead free solder alloys with the compositions of Sn-0.7Cu, Sn-3.5Ag, Sn-3.5Ag-0.75Cu, Sn-2.0Ag-0.7Cu-3.0Bi were applied to the 48 BGA packages, and then it was discussed for the shear strength at the solder joints as the hardness and the composition of the small solder ball. As a result of experiments, the high degree of hardness with the displacement of 0.043 mm was obtained in Sn-2.0Ag-0.7Cu-3.0Bi. The shear strength of the lead free solder was higher than that of Sn-37Pb solder, and it can be obtained the maximum value of about 52% in Sn-2.0Ag-0.7Cu-3.0Bi.

• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.4
• /
• pp.1-9
• /
• 2011

Understanding the void characterization in the solder joints has become more important because of the application of lead free solder materials and its reliability in electronic packaging technology. According to the JEDEC 217 standard, it describes void types formed in the solder joints, and divides into some categories depending on the void position and formation cause. Based on the previous papers and the standards related to the void, reliability of the BGA solder joints is determined by the size of void, as well as the location of void inside the BGA solder ball. Prior to reflow soldering process, OSP(organic surface preservative) finished Cu electrode was exposed under $85^{\circ}C$/60%RH(relative humidity) for 168 h. Voids induced by the exposure of $85^{\circ}C$/60%RH became larger and bigger with increasing aging times. The void position has more influence on mechanical strength property than the amount of void growth does.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2001.09a
• /
• pp.121-145
• /
• 2001

Chip Size Packages (CSP) are now widely used in high speed DRAM. The major driving farce of CSP development is its superior electrical performance than that of conventional package. However, the power dissipation of high speed DRAM like DDR or RAMBUS DRAM chip reaches up to near 2W. This fact makes the thermal management methods in DRAM package be more carefully considered. In this study, the thermal performances of 3 type CSPs named $\mu-BGA$^{TM}$$ $UltraCSP^{TM}$ and OmegaCSP$^{TM}$ were measured under the JEDEC specifications and their thermal characteristics were of a simulation model utilizing CFD and FEM code. The results show that there is a good agreement between the simulation and measurement within Max. 10% of $\circledM_{ja}$. And they show the wafer level CSPs have a superior thermal performance than that of $\mu-BGA.$ Especially the analysis results show that the thermal performance of wafer level CSPs are excellent fur modulo level in real operational mode without any heat sink.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.11a
• /
• pp.28-32
• /
• 2003

Thermo-mechanical behavior of a ceramic ball grid array(CBGA) package assembly and wire bond ball grid array(WB-PBGA) package assemblies are characterized by high sensitive moire interferometry. Moire fringe patterns are recorded and analyzed at various temperatures in a temperature cycle. Thermal-history dependent analyses of global and local deformations are presented, and bending deformation(warpage) of the package and shear strain in the rightmost solder ball are discussed. A significant non-linear global behavior is documented due to stress relaxation at high temperature. The locations of the critical solder ball in WB-PBGA package assemblies are documented.