• Title/Summary/Keyword: 루프 대역폭 조절

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Design of a Internal Loop Antenna for Multi-band Mobile Handset Applications (다중 대역 이동 통신 단말기용 내장형 루프 안테나 설계)

  • Lee Young-Joong;Lee Jin-Sung;Jung Byungwoon;Park Myun-Joo;Lee Byungje
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.9 s.100
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    • pp.917-925
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    • 2005
  • In this paper, the quad-band antenna for mobile handsets is proposed and developed. The operating frequency bands include GSM(880 MHz${\~}$960 MHz), GPS(1,575 MHz$\pm$10 MHz), DCS(1,710 MHz${\~}$l,880MHz), and PCS(1,850 MHz${\~}$l,990 MHz). The proposed antenna consists of a feed line, a shorting post, and a radiating element of the feed loop. The multi-band operation is achieved by using the fundamental and higher resonant modes of the radiating element. Based on analysis of the current distribution on the radiator, the resonant frequency of each mode can be adjusted by adding the different sizes of slots on the radiator. The radiator of the feed loop is designed to be symmetrical so that the energy is symmetrically distributed on the radiator, which results in omni-directional radiation pattern. The ground plane under the radiator is removed in order to improve the bandwidth. The measured impedance bandwidths are $10.1\%$ in GSM band(VSWR<2.5), $26.8\%$ in GPS band, and DCS/US-PCS bands(VSWR<2.5), respectively. The maximum gains on the H-plane of the fabricated antenna are measured about -0.37 dBi${\~}$2.55 dBi for all operating frequency bands.

A PDFF Position Control using Non-linear Compensator (비선형 보상기를 이용한 PDFF 위치제어)

  • 안영주;이형기
    • Journal of the Institute of Convergence Signal Processing
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    • v.3 no.4
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    • pp.49-56
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    • 2002
  • In this paper, a new controller using non-linear compensator for position control is presented, which we can satisfy the given specifications more easily than the existing one. We suggest an improved PDFE(Integral with Proportional-Derivative-plus-Feedforward) controller by which both phase margin and bandwidth are controlled simultaneously in the controller design problem. Replacing the feed forward term in the PDFF system with a CDIDF(Complex Dual Input Describing Function), the desired phase margin is obtained without diminishing the bandwidth of the closed loop system. The effectiveness of the proposed controller is confirmed through simulations and experiments. As The results of these, we know that it is possible to adjust overall specifications by varying parameters in the improved PDFF system.

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Synchronization performance optimization using adaptive bandwidth filter and average power controller over DTV system (DTV시스템에서 평균 파워 조절기와 추정 옵셋 변화율에 따른 대역폭 조절 필터를 이용한 동기 성능 최적화)

  • Nam, Wan-Ju;Lee, Sung-Jun;Sohn, Sung-Hwan;Kim, Jae-Moung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.5
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    • pp.45-53
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    • 2007
  • To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

Improved negative capacitance circuit stable with a low gain margin (이득 여유가 작아도 안정한 개선된 네가티브 커패시턴스 회로)

  • 김영필;황인덕
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.6
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    • pp.68-77
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    • 2003
  • An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

A CMOS Intermediate-Frequency Transceiver IC for Wireless Local Loop (무선가입자망용 CMOS 중간주파수처리 집적회로)

  • 김종문;이재헌;송호준
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.8A
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    • pp.1252-1258
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    • 1999
  • This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

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On the Phase Variation and Implementation of If Module for WLL CDMA System (WLL용 CDMA 시스템 IF 모듈의 구현 및 위상 특성)

  • 강병권;김선형
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.4 no.1
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    • pp.219-226
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    • 2000
  • In this paper, we design and implement a IF(intermediate frequency) module for WLL(wireless local loop) CDMA(code division multiple access) basestation. The implemented IF transceiver is consists of transmitter, receiver and local oscillator. The considered signal bandwidth is 10 MHz and the local carrier frequency is 40 MHz. As test results, the If transmitter output power is -5dBm $\pm3dB$when the baseband input is -10dBm $\pm3dB$, and the IF receiver output power is -10dBm $\pm3dB$when the IF input is -5dBm $\pm3dB$. Also the AGC(automatic gain control) circuit has dynamic range of 9 dB from -7dBm to +2dBm with output power 2dBm. And the group delay characteristic is analyzed by comparing the phase delay from 1 MHz to 5 MHz and the phase distortion is very low. We can conclude that this IF system can be applied to high speed data rate communication system.

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