• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.100-105
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• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1154-1162
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• 2016

This paper proposes a fast-transient digital LDO(Low dropout) regulator with binary-weighted current control technique. Conventional digital LDO takes a long time to stabilize the output voltage, because it controls the amount of current step by step, thus ringing problem is generated. Binary-weighted current control technique rapidly stabilizes output voltage by removing the ringing problem. When output voltage reliably reaches the target voltage, It added the FRZ mode(Freeze) to stop the operation of digital LDO. The proposed fast response digital LDO is used with a slow response DC-DC converter in the system which rapidly changes output voltage. The proposed digital controller circuit area was reduced by 56% compared to conventional bidirectional shift register, and the ripple voltage was reduced by 87%. A chip was implemented with a $0.18{\mu}F$ CMOS process. The settling time is $3.1{\mu}F$ and the voltage ripple is 6.2mV when $1{\mu}F$ output capacitor is used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.833-838
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• 2011

RFID system in manufacturing industry is used to collect, categorize, and process the data of products. To install RFID system for a large factory, a large amount of wired data communication network is necessary for RS232 communication. If the installed location of RFID system in the factory is changed or extended, a reinstallment is required for the already installed wired data network. A large amount of time/financial reinvestment is necessary for such reinstallation. By using wireless data communication network, however, the initial installation and reinstallation are very simple. In this paper, we implemented a wireless communication system and RFID system. We used the CC1020 chip for wireless communication system and EM4095 chip for RFID system. CC1020 chip enables highly-reliable data communication, and by setting a simple status register, it can switch between transmitting/receiving status and it can choose the desired frequency of either 400 MHz or 900 MHz. Also, Communication range is 50 m, if external antenna is used. EM4095 is a chip for RFID reader system with the carrier frequency of 125 KHz. This chip can implement the reader system by connecting a small number of components. And EM4100 was used for RFID system. EM4100 is read-only type. Atmega128 is used to control a wireless communication system and RFID system. We confirm that the system can communicate without error up to 50 m from sender. In the paper, the circuit diagram and operation program for CC1020 and RFID system are presented. The system used in the experiment is shown in pictures, and the data movement pattern of CC1020 is shown in the diagram, and the performance of each transmission method is presented.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.36-42
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• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.