• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.25-27
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• 2001

설계 재활용을 위하여서는, 반도체 지적 소유권(Intellectual property)의 표준화와 더불어 레이아웃 자동 이식에 관한 연구와 상품화가 필수적이다. 본 논문은 반도체 설계 형식 중에서 생산 공정과 밀접한 레이아웃 형식의 회로도면 처리를 자동화하여 설계와 생산 시간을 혁신적으로 단축하기 위한 연구이다. 레이아웃 형식은 특성상 도형(폴리곤)으로 구성되어 있으며, 레이아웃 형태에서 다양한 도형의 중첩이 반도체의 트랜지스터, 저항, 캐피시터를 표현함으로써, 반도체 지적소유권의 한 형식으로 자주 활용되고 있다. 본 논문은 반도체 레이아웃 이식 소프트웨어 시스템의 내부 기능에 관한 설명과 처리 능력과 속도를 높이기 위한 알고리즘의 제안과 벤치마킹 결과를 보여 주고 있다. 비교 결과, 자원의 최적 활용(41%)으로 대용량의 처리 가능성을 보여 주고 있으며, 처리 속도는 평균 27배로써 이전의 벤치마킹 회로를 더욱 크게 하여 그 결과를 보여 주고 있다. 이러한 비교 우위는 본 논문에 포함된 소자 처리 알고리즘과 그래프를 이용한 컴팩션 알고리즘에 기인한다. 지면상의 연유로, 참고1에서는 기능 설명을, 본 논문은 알고리즘의 구현에 관한 설명을 중점적으로 기술한다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.5
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• pp.95-102
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• 2013

In metabolomics, metabolic pathway is represented by well-displayed graph. Metabolic pathways, especially, have a complex binding structure, which makes the graphical representation hard to visualize. There is a problem that edge crossings exponentially increase as the number of nodes grows. To apply automatic graph layout techniques to the genome-scale metabolic flow of metabolism domains, it is very important to reduce unnecessary edge crossing on a metabolic pathway layout. we proposed a metabolic pathway layout algorithm based on 2-layer layout. Our algorithm searches any meaningful component existing in a pathway, such as circular components, highly connected nodes, and the components are drawn in upper layer. Then the remaining subgraphs except meaningful components are drawn in lower layer by utilizing a new radial layout algorithm. It reduces ultimately reduced the number of edge crossings. This algorithm is the basis of flexible analysis for metabolic pathways.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.61-63
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• 2006

본 논문은 온톨로지를 이용하여 단백질 상호작용 네트워크를 개념적으로 분류하여 레이아웃하는 방법을 제안한다. 상호작용 네트워크를 이루는 단백질은 온톨로지의 표준 통제 용어에 대한 주석 정보를 가지고 있으므로 동일 분류에 해당하는 통제 용어를 가지고 있는 단백질들은 근접한 곳에 위치하도록 레이아웃한다. 이는 기존 물리적 레이아웃에 기능별 그룹화를 해줌으로써 복잡한 네트워크를 개념적으로 분석할 수 있도록 한다. 또한, 동일 분류에 속하는 단백질들을 한 노드로 대응하여 레이아웃 알고리즘을 수행함으로써 기존의 그래프표현 알고리즘 보다 빠르게 시각화할 수 있다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.2120-2132
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• 1997

A layout automation system for analog integrated circuits is proposed. The implemented system performs full-custom analog layout under the analog layout constraints. In order to overcome the demerits of conventional analog layout systems, parameterized module library is proposed. The system can support complex analog layout modules, resulting in a maximum expandability of the system. Moreover, modified dynamic multi-path algorithm is developed by enhancing the conventional Dijkstra algorithm. Several benchmark circuits such as comparator, op amp, and filter was tested by the system. Layout results compared to OPASYN show well-merging layout and interdigitized layout module.

• Journal of Software Assessment and Valuation
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• v.17 no.2
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• pp.151-159
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• 2021

To derive grid lines for analyzing a table layout, line image enhancement techniques are studying such as various filtering or morphology methods. In spite of line image enhancement, it is still hard to extract line components and to express table cell's layout logically in which the cutting points are exist on the line or the tables are skewing . In this paper, we proposed a line tracking algorithm to extract line components under the cutting points on the line or the skewing lines. The table document layout analysis algorithm is prepared by searching grid-lines, line crossing points and gird-cell using line tracking algorithm. Simulation results show that the proposed method derive 96.4% table document analysis result with average 0.41sec processing times.

• Journal of the Korea Society of Computer and Information
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• v.18 no.6
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• pp.71-79
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• 2013

Metabolic pathway, represented by well-displayed graph, have a complex binding structure, which makes the graphical representation hard to visualize. To apply automatic graph layout techniques to the genome-scale metabolic flow of metabolism domains, it is very important to reduce unnecessary edge crossing on a metabolic pathway layout. we proposed a metabolic pathway layout algorithm based on 3-layer layout. Our algorithm searches any meaningful component existing in a pathway, such as circular components, highly connected nodes, and the components are drawn in middle layer. Then the remaining subgraphs except meaningful components are drawn in upper and lower layer by utilizing a new radial layout algorithm. It reduces ultimately reduced the number of edge crossings. Our algorithm solve the problem that edge crossings exponentially increase as the number of nodes grows.

• ETRI Journal
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• v.10 no.3
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• pp.193-211
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• 1988

집적 회로(integrated circuit)의 제작시 설계 규칙에 유연성이 있는 심볼릭 레이아웃 방식의 시스팀 구성을 칩 설계에 적용하는 경우 그 방법을 알아 보았으며, 시스팀의 툴들로서 graphical 에디터의 명령어, 컴팩터의 알고리즘 그리고 영역 탐색에 사용되는 데이터 구조 등을 알아보았다.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07b
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• pp.250-252
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• 2005

기존의 레이아웃 알고리즘은 경로의 가독성과 속도 등에 주안점을 두어 개발되었다. 따라서 이러한 시스템의 경우 노드수가 증가할수록 에지 크로싱이 기하급수적으로 증가하는 문제가 있는데, genome scale에서의 대사 경로를 연구하기 위해서는 대사 경로 그래프 레이아웃 상에 나타나는 에지 크로싱을 줄이는 것이 시각화의 매우 중요한 부분이다. 대사 경로는 효소에 의한 화합물 간의 변화를 보여주는 네트워크로서, 대부분 척도 없는 네트워크 구조를 갖는다는 것이 알려져 있다. 이러한 대사 경로의 구조적 특징을 고려하여 에지 크로싱을 최소화하는 대사 경로 레이아웃 방법을 제안하고, 그 결과 노드수의 증가에 따른 에지 크로싱의 급격한 증가현상이 $37\~40\%$의 감소된 결과를 나타냈으며, 노드수가 증가하더라도 에지 크로싱이 오히려 감소하는 경우도 관찰되었다.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.202-213
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• 2007

A network is an important model widely used in natural and social science as well as engineering. To analyze these networks easily it is necessary that we should layout the features of networks visually. These Graph-Layout researches have been performed recently according to the development of the computer technology. Among them, the Scale-free Network that stands out in these days is widely used in analyzing and understanding the complicated situations in various fields. The Scale-free Network is featured in two points. The first, the number of link(Degree) shows the Power-function distribution. The second, the network has the hub that has multiple links. Consequently, it is important for us to represent the hub visually in Scale-free Network but the existing Graph-layout algorithms only represent clusters for the present. Therefor in this thesis we suggest Graph-layout algorithm that effectively presents the Scale-free network. The Hubity(hub+ity) repulsive force between hubs in suggested algorithm in this thesis is in inverse proportion to the distance, and if the degree of hubs increases in a times the Hubity repulsive force between hubs is ${\alpha}^{\gamma}$ times (${\gamma}$??is a connection line index). Also, if the algorithm has the counter that controls the force in proportion to the total node number and the total link number, The Hubity repulsive force is independent of the scale of a network. The proposed algorithm is compared with Graph-layout algorithm through an experiment. The experimental process is as follows: First of all, make out the hub that exists in the network or not. Check out the connection line index to recognize the existence of hub, and then if the value of connection line index is between 2 and 3, then conclude the Scale-free network that has a hub. And then use the suggested algorithm. In result, We validated that the proposed Graph-layout algorithm showed the Scale-free network more effectively than the existing cluster-centered algorithms[Noack, etc.].

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.59-66
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• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.