• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1555_1556
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• 2009

전자기기에서 외부 Console로 사용되는 Touch Pad의 입력오류를 줄이기 위해서는 안정된 전원의 공급이 필요하다, 전원에서 발생하는 노이즈는 PDN(Power Delivery Network)의 임피던스에 의해서 발생하며, 이들 노이즈를 줄이기 위해서는 decoupling capacitor의 적절한 수량과 위치를 선정하여, PDN의 임피던스를 최소화해야 한다. 본 논문에서는 임피던스의 최소화를 위해서 Full-wave 시뮬레이션을 이용해서 임피던스 특성을 분석하고, VNA(Vector Network Analyzer)를 이용하여 주파수에 대한 PDN 임피던스를 측정하고, Touch Pad 구동용 지그를 이용해서 Time Domain에서의 임피던스 저감에 따른 노이즈 특성을 분석 비교하였다.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.11a
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• pp.367-370
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• 2005

This paper investigated the sound characteristics in an apartment complex. The field measurement was conducted in order to examine the acoustical characteristics of the apartment complex in situ. As a result, it shows that there are around 3 sec. reverberation time and the additional sound reinforcements at the area of high height due to the surrounded buildings. Thus, 1:50 Scale model measurement and Raynoise computer simulation were carried out with insertion of the parapet and the canopy on the balcony. In case of a single building, the parapet was effective to reduce noise level at low floor levels, and the canopy was effective to reduce noise level at high floor levels. But it also shows that both the parapet and the canopy were not effective to reduce noise level at middle floor levels. In case of an apartment complex, the canopy was less effective to reduce noise level at each floor in comparison with case of the single building.

• Journal of the Korean Society of Radiology
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• v.14 no.7
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• pp.937-946
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• 2020

The grating interferometer provides the differential phase contrast image of an phase object due to refraction of the wavefront by the object, and it needs to be converted to the phase contrast image. The line-integration process to obtain the phase contrast image from a differential phase contrast image accumulates noise and generate stripe artifacts. The stripe artifacts have noise and distortion increases to the integration direction in the line-integrated phase contrast image. In this study, we have configured and compared several machine learning methods to reduce the artifacts. The machine learning methods have been applied to simulated numerical phantoms as well as experimental data from the X-ray and neutron grating interferometer for comparison. As a result, the combination of the wavelet preprocessing and machine learning method (WCNN) has shown to be the most effective.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.