• Title/Summary/Keyword: 레벨 3

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Output Filler Design for Noise Reduction of Induction Motor Drive System using H-Bridge 7-Level Inverters (H-Bridge 7레벨 인버터를 이용한 유도전동기 구동시스템의 노이즈 저감을 위한 출력 필터설계)

  • Kim, Soo-Hong;Ahn, Young-Oh;Kim, Yoon-Ho;Bang, Sang-Seok;Kim, Kwang-Seob
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.20 no.3
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    • pp.36-44
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    • 2006
  • In general, the generated harmonics and noise of the PWM inverter are affected by PWM switching method, switching frequency, dv/dt and di/dt. Since multilevel inverters are often applied to the high power system, and operates with low switching frequency, theyproduce large size of harmonic contents and noise. Thus it is necessary to install output filters in the multilevel inverter. In this paper a filter design approach for the harmonic and noise reduction the three phase induction motor driving system using H-bridge 7-level inverter system is presented. The passive filter that has low cost and simple structure and can effectively reduce harmonics and noise, is designed and applied to the three phase induction motor drive having multilevel inverter system. The designed system is implemented and verified by simulation and experiments.

Design of digital clock level translator with 50% duty ratio from small sinusoidal input (작은 정현파입력의 50% Duty Ratio 디지털 클럭레벨 변환기 설계)

  • Park, Mun-Yang;Lee, Jong-Ryul;Kim, Ook;Song, Won-Chul;Kim, Kyung-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.8
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    • pp.2064-2071
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    • 1998
  • A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

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Performance Analysis for Digital watermarking using Quad-Tree Algorithm based on Wavelet Packet (웨이블렛 패킷 기반 쿼드트리 알고리즘을 이용한 디지털 워터마킹의 성능 분석)

  • Chu, Hyung-Suk;Kim, Han-Kil;An, Chong-Koo
    • Journal of the Institute of Convergence Signal Processing
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    • v.11 no.4
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    • pp.310-319
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    • 2010
  • In this paper, digital watermarking method using wavelet transform and quad-tree algorithm is proposed. The proposed algorithm transforms the input image by DWT(Discrete Wavelet Transform) and AWPT(Adaptive Wavelet Packet Transform), inserts the watermark by quad-tree algorithm and the Cox's algorithm. The simulation for performance analysis of the proposed algorithm is implemented about the effect of embedding watermark in each subband coefficient (HH, LH, HL) of DWT, each DWT level, and each AWPT level. The simulation result by using DWT is compared with that using AWPT in the proposed algorithm. In addition, the effect of embedding watermark in the lowest frequency band (LL) is simulated. As a simulation result using DWT, the watermarking performance of simultaneously embedding in HH, LH, and HL band of DWT(6 level) is better than that of different cases. The result of AWPT(3 level) improves the correlation value compared to that of DWT(3 level). In addition, insertion the watermark to the LL band about 30~60% of all watermarks improves the correlation value while PSNR performance decreases 1~2dB.

Cell Marking Priority Control Considering User Level Priority in ATM Network (ATM 네트워크에서 사용자 레벨 우선 순위를 고려한 셀 마킹 및 우선 순위 제어)

  • O, Chang-Se;Kim, Tae-Yun
    • The Transactions of the Korea Information Processing Society
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    • v.1 no.4
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    • pp.490-501
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    • 1994
  • In this study the problems of cell marking method used in the field of ATM network traffic control are presented. Also an extended cell marking method considering the user level priority is proposed. The conventional traffic monitoring schemes set the CLP bit of a cell to 1 only under the circumstance of the violation of traffic contract. It causes that the number of low level cells increases and the levels of cells are lowered regardless of the user level priority. The three level priority control method combining FCI bit with CLP bit has also been proposed. It divides CLP=0 cells into two levels. Consequently, the proposed method preserves more cells in high level than the conventional one and the real loss of high level cells can be reduced. The performance of the proposed scheme has also been analyzed by the PBS(partial buffer sharing) with two thresholds for the proposed three levels. The result shows that the PBS with two thresholds can give more efficient control than the scheme with no priority, or the PBS with one threshold.

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A Method on the Improvement of the Signal Processing Calculation Structure of the Remote Measurement Level Meter (원격 측정 레벨계의 신호처리 연산 구조 개선 방법)

  • Park, Dongkun;Lee, Kijun
    • Korean Journal of Remote Sensing
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    • v.35 no.3
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    • pp.389-400
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    • 2019
  • Level meters are non-invasively capable of measuring the level of the medium, and a growing variety of level meters are being used in the industry in connection with safety and maintenance. The level meter can be measured according to various kinds of medium such as solid medium such as coal, flour, rice and liquid medium such as water and petroleum. In order to reduce the error depending on the medium, the measurement using the Doppler Effect can compensate the measurement error, However, the number of signal processing steps is increased, the operation speed is further increased, the hardware complexity increases, and a high cost structure is required. In this paper, we propose a method to improve the signal processing operation structure of the remote measurement level meter to reduce the amount of computation and the resource usage of the required FPGA.

Implementation of Gray-to-Gray 3D Crosstalk Reduction using Look-Up Table and Sub-Field Mapping (룩업 테이블 및 서브필드 맵핑을 이용한 계조 레벨 간 3D 크로스토크 저감 기술 구현)

  • Hong, Jae-Geun;Chung, Hae
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.10
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    • pp.928-936
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    • 2013
  • 3D crosstalk is one of the disturbing things to recognize 3D images. This is caused by the phenomenon that input image for left eye is transferred at the right eye and right eye is transferred at the left eye because of the imperfect isolation by the device characteristics. In this paper, we review the 3D PDP (Plasma Display Panel) operation using active shutter glasses and crosstalk measurement method and investigate the major cause of 3D crosstalk and extend conventional 3D crosstalk using full white and full black image input to Gray-to-Gray (GtoG) 3D crosstalk. We suggest a specific method to reduce Gray-to-Gray 3D crosstalk by using Look up Table (LUT) and sub-field mapping in PDP. And then, we verify the method by measuring GtoG 3D crosstalk rate through specific test images and numerical results.

Parallel Processing Techniques for Computer Vision Tasks (컴퓨터 비전 태스크에 대한 병렬 처리 기술 동향)

  • Chung, Y.;Park, J.-W.
    • Electronics and Telecommunications Trends
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    • v.13 no.6 s.54
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    • pp.13-33
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    • 1998
  • 최근 2, 3년 사이에 국내에서도 많은 병렬 머신이 도입되면서 병렬처리에 대한 관심이 높아지고 있다. 본 고에서는 미국에서 최근 고성능 컴퓨팅 기술 개발 사업의 일환으로 추진하고 있는 Grand Challenge Problems에 속하지만 다른 과학계산 응용과는 특성이 다른 컴퓨터 비전 태스크를 병렬화 하는 여러 가지 방법에 대해 살펴본다. 먼저 컴퓨터 비전 태스크와 이를 병렬화 할 때 일반적인 특징에 대해서 설명한다. 그리고 하위 레벨(low-level), 중간 레벨(intermediate-level), 상위 레벨(high-level) 태스크 각각을 예로 들면서 병렬처리 방법에 대해 설명한 후, 여러 레벨의 비전 태스크를 종합적으로 병렬화 할 때 제기되는 문제로서 태스크 병렬성(task parallelism) 및 이질적 처리(heterogeneous processing)에 대해서 알아본다. 마지막으로 이러한 컴퓨터 비전 태스크에서의 여러가지 병렬처리에 대한 벤치마크에 대하여 살펴본다.

Transformation of Measured Blasting Sound Data to Sound Level by Digital Filter (디지털 필터를 이용한 소음의 변환 연구)

  • Kim, Yong-Kuk;Kim, Sik;Lee, Sang-Eun;Yang, Hyung-Sik
    • Explosives and Blasting
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    • v.18 no.3
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    • pp.77-82
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    • 2000
  • 현재까지 폭풍압은 음압과 음압레벨로 측정되어 왔다. 그러나 발파 소음에 의한 인체의 반응이나 가축의 피해 산정 등의 문제에서는 현행 소음진동규제법에서 명시하는 바, 인체의 청감보정이 이루어진 소음레벨을 사용하므로 변환문제가 발생한다. 본 연구에서는 발파 진동 계측기기로 계측한 데이터를 디지털 필터로 처리하여, 소음레벨로 변환하는 프로그램을 개발하고, 이를 실제 발파계측결과에 적용하였다. 그 결과, 국내에서 널리 사용되고 있는 Instantel Inc,의 Blast1ate series에서 계측된 소음데이터가 정밀도 높은 소음레벨로 변환이 가능하였다. 비슷한 정밀도로 계측결과를 ASCII file로 송출할 수 있는 기종에서 계측된 자료도 같은 정도로 처리할 수 있을 것으로 판정되었다.

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Power spectrum of a Multi-Level Inverter Employing a Multi-Carrier Random PWM Method (멀티 캐리어 Random PWM기법을 적용한 멀티 레벨 인버터의 파워 스펙트럼)

  • Kim, J.N.;Oh, S.Y.;Lim, Y.C.;Jung, Y.G.
    • Proceedings of the KIEE Conference
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    • 2004.04a
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    • pp.150-154
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    • 2004
  • 본 연구에서는 멀티 레벨 인버터의 파워 스펙트럼을 광대역으로 분산시키기 위한 멀티 캐리어 Random PWM기법을 제안하였다. PD(phase disposition)방식 및 H(hybrid)방식의 멀티 캐리어 Random PWM을 단상 cascade H-브리지 멀티 레벨 인버터와 3상 hybrid 멀티 레벨 인버터에 적용하였다. 각 방식에 따른 출력 전압/전류 파형 및 고조파 스펙트럼을 PSIM에 의하여 확인 하였으며, 제안된 방식의 타당성을 입증할 수 있었다.

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Analysis of output voltage characteristic according to input voltage in hybrid multilevel inverter (혼합형 멀티레벨 인버터의 입력전압원 크기에 따른 출력전압 특성분석)

  • Hong, Un-Taek;Choi, Won-Kyun;Kwon, Cheol-Soon;Hyun, Seok-Hwan;Kang, Feel-Soon
    • Proceedings of the KIPE Conference
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    • 2010.07a
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    • pp.502-504
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    • 2010
  • 본 논문에서는 풀-브리지 모듈과 양방향 스위치를 가지는 5-레벨 인버터를 다단 결합시켜 15-레벨의 출력을 형성할 수 있는 혼합형 멀티레벨 인버터를 제안한다. 제안된 회로의 입력전압원의 크기가 서로 동일한 경우와 3의 배수 형태를 가지는 경우에 대한 특성을 분석하고 시뮬레이션 및 실험을 통해 가장 효율적인 혼합형 회로 구성을 제시한다.

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