• Journal of IKEEE
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• v.18 no.2
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• pp.198-205
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• 2014

As the development of information technology, the interests in tiny applications such as wearable devices, portable devices and RFID are increased and the importance of low-area encryption circuit is emphasized. This paper proposes a compact architecture of AES-based encryption circuit suitable for tiny applications. The circuit area is reduced by minimizing storage space and sharing computation resources. The synthesized gate-level circuit using 65nm standard cell library consists of 2,241 gates and two $8{\times}16$-bit SRAMs. It can process data at a rate of 50.57Mbits per second. Therefore, the proposed encryption circuit is suitable for various applications requiring very small encryption circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.875-879
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• 2002

CPL is a technique that serves various additional service in Internet telephony such as call forwarding, call blocking etc. IETF IPTEL working group developed this CPL standard. Users could request various additional services such as call forwarding, call blocking etc. by registering XML scripts to location servers. This paper would describe the design and the implementation skill of SIP proxy server that support these improved functionalities in detail. SIP registrar and SIP proxy server are designed and implemented in Linux platform because this platform serves fast and low cost development environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2120-2130
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• 1998

This paper concerns a design of programmable MPEG decoder for video processing by object unit on network. The decoder can process video data effectively by a embedded controller with stack buffers for supporting OOP (Object-Oriented Programming). The controller offers extended instructions that process several data types including 32bit integer type. In addition to that, we have a vector processor, in this decoder that can execute advanced compensation and prediction by half pixel and SA(Shape Adaptive)-IDCT of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We verified the decoder with $0.6\mu\textrm{m}$ 5-Volt CMOS COMPASS library.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.5
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• pp.815-825
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• 2015

DNP3(Distributed Network Protocol) is one of the most representative protocols which is used in SCADA(Supervisory Control and Data Acquisition) system. IEC 62351 is listing the integrity, confidentiality, availability and non-repudiation or accountability as the security requirement. However, IEEE Std. 1815 that is DNP3 standards does not define a mechanism for non-repudiation or accountability. In this paper, we propose a non-repudiation of origin technique about the sender of critical ASDU and implement the proposed scheme using software such as OpenSSL and SCADA source code library.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.4C
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• pp.321-328
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• 2012

The Mobile device like smart phone is a small computing device and easy to carry around. The Mobile devices are wildly being used as desktop personal computer and can served individual services. Because of compatibility of applications working on mobile devices are not good, so developer need to develop it that match changes in platform fetures. In this paper, we design and implementate ubiquitous healthcare monitoring system that can be runs on many different platforms using HTML5 as a standard web development language and jQuery as a javascript library. Ubiquitous healthcare monitoring system is runs on on many different platforms like mobile platforms and desktop web browsers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.62-71
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• 2002

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. the instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. The proposed DPU (Data Processing Unit) supporting the instructions shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 ${\mu}m$ standard cell library. The maximum operating clock frequency is about 144.5 MHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.5
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• pp.41-49
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• 2004

As a means of overcoming the linguistic barrier between different languages in the Internet cyberspace, a sign-language communication system has been proposed. However, the system supports avatars having the same model structure so that it is difficult to communicate between different avatar models. Therefore, in this paper, we propose a new gesture communication system in which different avatars models can communicate with each other by using a FBML (Facial Body Markup Language). Using the FBML, we define a standard document format that contains the messages to be transferred between models, where the document includes the action units of facial expression and the joint angles of gesture animation. The proposed system is implemented with Visual C++ and Open Inventor on Windows platforms. The experimental results demonstrate a possibility that the method could be used as an efficient means to overcome the linguistic problem.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2154-2162
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography for smart card security. The scaler multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scala multiplication on finite field, the non-adjacent format (NAF) conversion algorithm which is based on complementary recoding is adopted. The scalar multiplier core synthesized with a 0.35-${\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smartcard security.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.2
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• pp.176-184
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• 1999

지금까지의 소프트웨어 기반 분산 공유 메모리(이하 DSM이라 칭함)시스템은 유닉스 워크스테이션 클러스터를 목표로 하는 것이 대부분이었다. 그러나 현재 Windows-NT 는 서버급 시스템과 PC 모두를 위한 운영체제로서 유닉스와 더불어 널리 사용되고 있는 실정이다. 본 논문에서는 Windows-NT 워크스테이션 클러스터 환경을 위한 DSM 시스템을 구현하고, 구현된 DSM 시스템의 성능 평가 결과를 제시한다. 구현된 DSM 시스템은 Win32 API와 표준 실행-시간 라이브러리를 이용해 구현되었기 때문에 모든 Windows-NT 워크스테이션에서 실행 가능하며 , 프로그래머는 몇 라인의 코드 추가만으로 DSM 시스템 상에서 수행되는 병렬 응용 프로그램을 작성할 수 있다. 워크스테이션 간의 상호연결망으로 범용성을 위해 이더넷 LAN을 지원하였고, 아울러 성능 향상을 위해 기가비트 SAN(System Area Network)도 지원하였다. 기가비트 SAN을 위한 하드웨어로는 Dolphin 사의 PCI-SCI 타입 제품인 Clustar를 사용하였다. 우리는 성능 평가를 통해, 구현된 DSM 시스템이 정확히 동작함은 물론 확장성이 뛰어나다는 것을 확인하였다. 특히 , 기가비트 SAN을 사용할 경우 일부 병렬 벤치 마크 프로그램에서는 노드 수 증가에 따라 성능이 거의 선형적으로 향상된다는 것을 알 수 있었다. 본 논문이 기여하는 바는 Windows-NT 기반 소프트웨어 DSM 시스템의 원천 기술을 확보함으로써 향후 Windows-NT 워크스테이션 클러스터 환경에서의 분산 및 병렬 처리 연구에 도움을 줄 수 있다는 점이다.

• KIISE Transactions on Computing Practices
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• v.21 no.8
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• pp.561-566
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• 2015

Hadoop is becoming widely adopted in scientific and commercial areas as an open-source distributed data processing framework. Recently, for real-time processing and analysis of data, an attempt to apply high-performance computing technologies to Hadoop is being made. In this paper, we have expanded the Hadoop Filesystem library to support Lustre, which is a popular high-performance parallel distributed filesystem, and implemented the Hadoop MapReduce execution environment over the Lustre filesystem. We analysed Hadoop MapReduce over Lustre by using Hadoop standard benchmark tools. We found that Hadoop MapReduce over Lustre execution has a performance 2-13 times better than a typical Hadoop MapReduce execution.