• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.119-124
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• 2009

In this paper, AMR-WB+ audio coder is implemented, in real-time, using Intel 400MHz Xscale PXA250 with 32bit RISC processor ARM9E-J(R)core. The assembly code for ARM9E-J(R)core is developed through the serial process of C code optimization, cross compile, assembly code manual optimization and adjusting the optimized code to Embedded Visual C++ platform. C code is trimmed on Visual C++ platform. Cross compile and assembly code manual optimization are performed on CodeWarrior with ARM compiler. Through these stages the code for both ARM EVM board and PDA is implemented. The average complexities of the code are 160.75MHz on encoder and 33.05MHz on decoder. In case of static link library(SLL), the required memories are 65.21Kbyte, 32.01Kbyte and 279.81Kbyte on encoder, decoder and common sources, respectively. The implemented coder is evaluated using 16 test vectors given by 3GPP to verify the bit-exactness of the coder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.39-48
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• 2004

Turbo codes, whose performance in bit error rate is close to the Shannon limit, have been adopted as a part of standard for the third-generation high-speed wireless data services. Iterative Turbo decoding results in decoding delay and high power consumption. As wireless communication systems can only use limited power supply, low power design techniques are essential for mobile device implementation. This paper proposes new effective criteria for stopping the iteration process in turbo decoding to reduce power consumption. By setting two stopping criteria, decodable threshold and undecodable threshold, we can effectively reduce the number of decoding iterations with only negligible error-correcting performance degradation. Simulation results show that the number of unsuccessful error-correction can be reduced by 89% and the number of decoding iterations can be reduced by 29% on the average among 12500 simulations when compared with those of an existing typical method.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• Journal of Korea Multimedia Society
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• v.8 no.10
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• pp.1403-1410
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• 2005

The synchronization problem is directly related to the quality of service in multimedia communication and especially in real-time communication. In this study, we found the cause of clock fluctuation between encoder and decoder in MPEG-2 system layer was that the standard decoder design only considered a fixed time delay component. To solve it, we proposed Extended-SRTS algorithm, which uses STC as service clock by synchronizing transport stream. As the result, we can improve the effect of frequency-drift, time-varying-network-jitter and packing-jitter and so on And by virtue of this algorithm, we can make low the dependency of network clock, which makes easy to synchronize and connect transparently at the ends point, we expect the proposed algorithm can be widely applied to the field of real -time multimedia communications.

• Journal of Korea Multimedia Society
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• v.10 no.8
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• pp.958-966
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• 2007

In this paper, we implement a sound-enhanced MPEG-1 audio decoder on embedded OS Platform. Low bit rate lossy audio codecs such as MP3, OGG, and AAC for mitigating the problems in storage space and network bandwidth suffer a major common problem such as a loss of high frequency fidelity of audio signal. This high frequency loss will reproduce only a band-limited low-frequency part of audio in the standard CD-quality audio. In order to overcome this problem, we embedded a sound enhancement algorithm into the MPEG-1 audio decoder and then the algorithms optimized according to the characteristic of the MPEG-1 audio layer I, II, III were implemented on an embedded OS platform. From the experimental results with spectrum analysis and listening test, we confirm the superiority of the proposed system compared to the standard MPEG-1 audio decoder.

• Journal of The Korean Association of Information Education
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• v.20 no.4
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• pp.333-340
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• 2016

When elementary students write their own sentences, it is often educationally beneficial to compare them with other people's similar sentences. However, it is impractical for use in most classrooms, because it is burdensome for teachers to look up all of the sentences written by students. To cope with this problem, we propose a novel approach for automatic selection of similar sentences based on a three-step process: 1) extracting the subword units from the word-level sentences, 2) training the model with the encoder-decoder architecture, and 3) using the approximate k-nearest neighbor search algorithm to find the similar sentences. Experimental results show that the proposed approach achieves the accuracy of 75% for our test data.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.18-24
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• 2010

In this paper, a new matrix decoding system using vector based Virtual Source Location Information (VSLI) is proposed as an alternative to the conventional Dolby Pro logic II/IIx system for reconstructing multi-channel output signals from matrix encoded two channel signals, Lt/Rt. This new matrix decoding system is composed of passive decoding part and active part. The passive part makes crude multi-channel signals using linear combination of the two encoded signals(Lt/Rt) and the active part enhances each channel regarding to the virtual source which is emergent in each inter channel. Since the virtual sources are related to the perceptual sound images in virtual sound field, the reconstructed multi-channel sound results in good dynamic perception and stable image localization. Moreover, the good channel separation is maintained with nonlinear trigonometric enhancing function.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.104-111
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• 2002

In this paper, we proposed the architecture of the decoder which implements the multi-view images decoding algorithm. The study of the hardware structure of the multi-view image processing has not been accomplished. The proposed multi-view images decoder operates in a three stage pipelined manner and extracts the depth of the pixels of the decoded image every clock. The multi-view images decoder consists of three modules, Node selector which transfers the value of the nodes repeatedly and Depth Extractor which extracts the depth of each pixel from the four values of the nodes and Affine transformer which generates the projecting position on the image plane from the values of the pixels and the specified viewpoint. The proposed architecture is designed and simulated by the Max+plus II design tool and the operating frequency is 30MHz. The image can be constructed in a real time by the decoder with the proposed architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2373-2379
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• 2015

COMS(Communication, Ocean and Meteorological Satellite), the first Korean geostationary meteorological satellite, provides free meteorological information through HRIT/LRIT(High/Low Rate Information Transmission) service. This work presents the development of data receiver circuit that is essential to the implementation of a low-cost meteorological information receiver system. The data receiver circuit processes the data units according to the specification of physical layer and data link layer of HRIT/LRIT service. For this purpose, the circuit consists of a Viterbi decoder, a sync. word detector, a derandomizer, a Reed-Solomon decoder and so on. The circuit also supports PCI express interface to pass the information data on to the host PC. The circuit was implemented on an FPGA(field programmable gate array) and its function was verified through simulations and hardware implementation.