• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1563-1570
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• 1999

This paper relates to the soft decision method with erasure technique in digital terrestrial television broadcasting system. The proposed decoder use the CSI derived from using the pilots in receiver. The active real(I) and imaginary(Q) data are transferred to the branch metric calculation block that decides the Euclidean distance for the soft decision decoding and also the estimated CSI values are transferred to the same block. After calculating the Euclidean distance for the soft decision decoding, the Euclidean distance of branch metric is multiplied by CSI. To do so, new branch metric values that consider each carrier state information are obtained. We simulated this method in better performance of about 0.15dB to 0.17dB and 2.2dB to 2.9dB in Rayleigh channel than that of the conventional soft decision Viterbi decoding with or without bit interleaver where the constellation is QPSK, 16-QAM and 64-QAM.

• Journal of the Korea Society of Computer and Information
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• v.25 no.5
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• pp.37-46
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• 2020

Recently, studies of facial attribute editing have obtained realistic results using generative adversarial net (GAN) and encoder-decoder structure. Spatial attention GAN (SaGAN), one of the latest researches, is the method that can change only desired attribute in a face image by spatial attention mechanism. However, sometimes unnatural results are obtained due to insufficient information on face areas. In this paper, we propose an improved SaGAN (MSaGAN) using a guide mask for learning and applying multitask learning approach to improve the limitations of the existing methods. Through extensive experiments, we evaluated the results of the facial attribute editing in therms of the mask loss function and the neural network structure. It has been shown that the proposed method can efficiently produce more natural results compared to the previous methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.10
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• pp.83-93
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• 1999

In MPEG-2 video standard, there are many parameters to support profiles and levels. It is necessary to verify that a decoder is compliant with the MPEG-2 standard. This paper proposes a design principle of the test bitstreams which confirms that an MPEG video decoder is correct by observing the final image of the decoder under test. The presented test bitstream is composed of two parts. The first part generates a test pattern by varying a selected test parameter. And the following predictive coded picture generates a complementary pattern to the previous image by motion compensation and DCT coefficients. Then it will result in a uniform pattern. We present several bitstreams following the proposed principle. Also we analyze and compare the characteristics of the test bitstreams presented in the MPEG conformance test and the proposed test bistreams.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1579-1588
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• 2014

The LAN method is the most widely used in domestic high-speed internet access and rapidly moving to 1 Gbps Ethernet from 100 Mbps one to provide high-speed services such as UHD TV. The 1000BASE-T PHY with 4 pairs UTP transmits a PAM-5 signal at the 125 MHz clock per each pair to achieve 1 Gbps rate. In order to correct errors over the channel, the transmitter uses a TCM which is combined the convolutional encoder and PAM-5, and the receiver uses the Viterbi decoder. In this paper, we implement a Viterbi decoder which can correct two pair errors and operate at the least 125 MHz clock speed. Finally, we will verify the error correction function and the operating speed of the implemented decoder with a logic analyzer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.36-44
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• 2003

This paper proposes a Viterbi decoding scheme without trace-back operations to reduce the amount of memory storing the survivor path information, and to increase the decoding speed. The proposed decoding scheme is a modified register exchange scheme, and is verified by a simulation to give the same results as those of the conventional decoders. It is compared with the conventional decoding schemes such as the trace-back and the register exchange scheme. The memory size of the proposed scheme is reduced to 1/(5 x constraint length) of that of the register exchange scheme, and the throughput is doubled compared with that of the trace-back scheme. A decoder with a code rate of 2/3, a constraint length, K＝3 and a trace-back depth of 15 is designed using VHDL and implemented in an FPGA. It is also shown that the modified register exchange scheme can be applied to a block decoding scheme.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.1-7
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• 2008

The general bus architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. Specially, as several masters do not concurrently receive the right of bus usage, the arbiter plays an important role in arbitrating between shared bus and masters. Fixed priority, round-robin, TDMA and Lottery methods are developed in general arbitration policies, which lead the efficiency of bus usage in shared bus. On the other hand, the bus architecture can be modified to maximize the system performance. In the paper, we propose the flying master bus architecture that supports the parallel bus communication and analyze its merits and demerits following various arbitration policies that are mentioned above, compared with normal shared bus. From the results of performance verification using TLM(Transaction Level Model), we find that more than 40% of the data communication performance improves, regardless of arbitration policies. As the flying master bus architecture advances its studies and applies various SoCs, it becomes the leading candidate of the high performance bus architecture.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.