• Title/Summary/Keyword: 디지털 주사 변환

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Multiplier Using CRT and Overlapped Multiple-bit Scanning Method (CRT와 중첩다중비트 주사기법을 접목한 승산기)

  • 김우완;장상동
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.12
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    • pp.749-755
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    • 2003
  • Digital signal processing hardware based in RNS is currently considered as an important method for high speed and low cost hardware realization. This research designs and implements the method for conversion from a specific residue number system with moduli of the from $(2^k-1, 2^k, 2^k+1)$ to a weighted number system. Then, it simulates the implementation using a overlapped multiple-bit scanning method in the process of CRT conversion. In conclusion, the simulation shows that the CRT method which is adopted in this research, performs arithmetic operations faster than the traditional approaches, due to advantages of parallel processing and carry-free arithmetic operation.

A Study on Simple chip Design that Convert Improved YUV signal to RGB signal (개선된 YUV신호를 RGB신호로 변환하는 단일칩 설계에 관한 연구)

  • Lee, Chi-Woo;Park, Sang-Bong;Jin, Hyun-Jun;Park, Nho-Kyung
    • Journal of IKEEE
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    • v.7 no.2 s.13
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    • pp.197-209
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    • 2003
  • A current TV out format is quite different from that of HDTV or PC monitor in encoding techniques. In other words, a conventional analog TV uses interlaced display while HDTV or PC monitor uses Non-interlaced / Progressive-scanned display. In order to encode image signals coming from devices that takes interlaced display format for progressive scanned display, a hardware logic in which scanning and interpolation algorithms are implemented is necessary. The ELA(Edge-Based Line Average) algorithm have been widely used because it provided good characteristics. In this study, the ADI(Adaptive De-interlacing Interpolation) algorithm using to improve the ELA algorithm which shows low quality in vertical edge detections and low efficiency of horizontal edge lines. With the De-interlacing ASIC chip that converts the interlaced Digital YUV to De-interlaced Digital RGB is designed. The VHDL is used for chip design.

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Signal Processor Design of Scanning Type Thermal Imaging System using IRFPA (주사방식 초점면 배열 열상장비의 신호처리기 설계)

  • Hong, S.M.;Yoon, E.S.;Yu, W.K.;Park, Y.C.;Lee, J.H.;Song, I.S.;Yum, Y.H.
    • Proceedings of the KIEE Conference
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    • 2004.07d
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    • pp.2600-2602
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    • 2004
  • 열상장비는 물체가 방출하는 적외선 영역의 미약한 에너지를 검출하여 눈에 보이는 영상으로 변환하는 장비이다. 주간과 동일한 영상을 야간에도 획득할 수 있기 때문에 야간 감시등 군사용 장비로 활용되지만 최근에는 송전선로의 이상 유무 판단, 저장 탱크의 저장량 확인, 사스 환자의 체열 검색 등 산업계와 의료계의 이용도 증가하고 있다. 본 논문에서는 최신 기술인 주사방식 초점면 배열 열상장비의 아날로그 및 디지털신호처리기 설계와 제작 기술을 다룬다. $480{\times}6$ 배열의 고밀도 검출 소자를 이용하여 고속, 저잡음 신호처리를 함으로써 안정된 열 영상을 실시간으로 획득하였다.

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Implementation of a backend system for real-time intravascular ultrasound imaging (실시간 혈관내초음파 영상을 위한 후단부 시스템 구현)

  • Park, Jun-Won;Moon, Ju-Young;Lee, Junsu;Chang, Jin Ho
    • The Journal of the Acoustical Society of Korea
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    • v.37 no.4
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    • pp.215-222
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    • 2018
  • This paper reports the development and performance evaluation of a backend system for real-time IVUS (Intravascular Ultrasound) imaging. The developed backend system was designed to minimize the amount of logic and memory usage by means of efficient LUTs (Look-up Tables), and it was implemented in a single FPGA (Field Programmable Gate Array) without using external memory. This makes it possible to implement the backend system that is less expensive, smaller, and lighter. The accuracy of the backend system implemented was evaluated by comparing the output of the FPGA with the result computed using a MATLAB program implemented in the same way as the VHDL (VHSIC Hardware Description Language) code. Based on the result of ex-vivo experiment using rabbit artery, the developed backend system was found to be suitable for real-time intravascular ultrasound imaging.

Development of Planar Active Electronically Scanned Array(AESA) Radar Prototype for Airborne Fighter (항공기용 평면형 능동 전자주사식 위상 배열(AESA) 레이더 프로토 타입 개발)

  • Chong, Min-Kil;Kim, Dong-Yoon;Kim, Sang-Keun;Chon, Sang-Mi;Na, Hyung-Gi
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.12
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    • pp.1380-1393
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    • 2010
  • This paper presents a design, fabrication and the test results of planar active electronically scanned array(AESA) radar prototype for airborne fighter applications using transmit/receive(T/R) module hybrid technology. LIG Nex1 developed a AESA radar prototype to obtain key technologies for airborne fighter's radar. The AESA radar prototype consists of a radiating array, T/R modules, a RF manifold, distributed power supplies, beam controllers, compact receivers with ADC(Analog-to-Digital Converter), a liquid-cooling unit, and an appropriate structure. The AESA antenna has a 590 mm-diameter, active-element area capable of containing 536 T/R modules. Each module is located to provide a triangle grid with $14.7\;mm{\times}19.5\;mm$ spacing among T/R modules. The array dissipates 1,554 watts, with a DC input of 2,310 watts when operated at the maximum transmit duty factor. The AESA radar prototype was tested on near-field chamber and the results become equal in expected beam pattern, providing the accurate and flexible control of antenna beam steering and beam shaping.