• Journal of Biomedical Engineering Research
• /
• v.20 no.6
• /
• pp.531-537
• /
• 1999

본 연구에서는 FFT와 파라메트릭 방법에 의한 혈류 추정방법을 연구하고 디지털 신호처리 프로세서를 이용하여 레이저 도플러 혈률계를 구현하였다. 레이저 도플러 혈류계는 피부의 모세혈류의 흐름을 측정할수 있는 장비로서 다양한 분야에 활용이 가능하다. 구현된시스템은 TI사의 TMS320C32 DSP를 사용하였으며, 전력 스펙트럼의 모멘트값을 이용하여 혈류를 추정하였다. 혈류 추정 값은 매 0.5초마다 그래픽 사용자 인터페이스를 통해서 표시하도록 하였다. 시스템의 성능을 평가하기 위해서 혈류 시뮬레이터에 흐르는 혈류를 계단함수, 삼각함수, 사인함수로 제어하여 그 결과를 비교하였으며 인체 부위에 따른 혈류를 측정하였다. 실험결과 구현된시스템의 혈류 추정성 및 재현성이 보장되고있음을 확인할수 있었다.

• Proceedings of the Korean Society of Computer Information Conference
• /
• 2014.01a
• /
• pp.31-34
• /
• 2014

모바일 프로세서와 모바일 운영체제의 발달에 따라 스마트폰에서도 멀티미디어 신호 처리를 실시간으로 처리가 가능해 졌다. 또한 스마트폰의 급격한 보급률의 증가 및 대중의 악기에 대한 관심이 높아졌다. 이러한 흐름에 따라 국내에 특히 많이 보급되어 있는 안드로이드 스마트폰을 이용하여 고비용의 멀티 이펙트를 대체할 수 있는 어플리케이션을 구현했다. 멀티 이펙트에는 디스토션, 오버드라이브, 딜레이, 에코, 플렌저, 코러스 및 비브라토를 포함하였으며, 구현 결과 매틀랩 시뮬레이션과 유사함을 보였다.

• Information and Communications Magazine
• /
• v.19 no.4
• /
• pp.53-61
• /
• 2002

세계는 현재 디지털 혁명에 의한 새로운 정보통신(IT) 서비스의 홍수에 직면해있다. '언제, 어디서나, 사용자의 요구에 맞추어'라는 말은 이미 모든 서비스 기술개발 분야에서 캐치프레이즈로 자리잡은지 오래 되었다. 통신은 기존 전화를 통한 음성 서비스 위주에서 점차 데이터 통신으로 무게 중심이 이동되고 있고, 방송도 단순한 영상물 중심의 프로그램 전달이 아닌 개인별 정보 전달 및 양방향 통신에 의한 부가서비스로 그 영역을 확장해가지고 있다. 이런 변화의 중심에는 역시 '디지털' 기술에 의해 가능한 '융합(Convergence)' 화를 위한 기술개발이 그 동력을 제공하고 있으며, 프로세서 , 메모리, 디스플레이, 모뎀 등 하드웨어의 발전과 함께 오디오비쥬얼 신호 압축 및 전송, 웹 문서처리 등 소프트웨어적인 기술 개발 및 표준화 결과를 상호 유기적이고 통합적으로 각 응용 서비스 시스템에 적용함으로써 가능해지고 있다. 본 고에서 데이터 방송, 지능형 방송 및 MPEG-21 멀티미디어 프레임워크 표준을 중심으로 방송의 입장에서 본 방송통신융합의 기술개발 현황과 전망에 대해 개괄해보기로 한다.

• Journal of Engineering Education Research
• /
• v.8 no.1
• /
• pp.5-19
• /
• 2005

This paper describes the design and fabrication of magnetic levitation kits for use in the hands on experiments of automatic control, digital control and microprocessor applications in the division of mechatronics in Samcheok university. The kits are developed inspired by MIT's design, but it is designed on the digital basis, whereas MIT's is designed on the analog basis. As a result, the kits can be monitored and controlled on the analog and digital control techniques. Furthermore, the cost of kit components is comparable or lower to that of MIT design. And the kits can be controlled with magnetic hall sensors and/or infrared sensors, which provides more versatile experience on the use of sensors and signal filtering to the students. The design is fabricated and tested by authors and will be provided to the students as lab projects. The kits will be intentionally presented with a device that is poorly instrumented and poorly compensated. And the students are expected to analyze sensor signal and controller performance, and then, perform compensator design and signal filtering.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.2 no.2
• /
• pp.35-40
• /
• 1997

The hysteresis control method has been frequently used for current control of power conversion equipments or motor drive systems. This method makes the measured signal follow the reference signal by changing the control signal whenever the error signal exceeds the preset band width. In this paper, hysteresis control method with fast response characteristics is applied for active noise control to suppress acoustic noise. Both Pentium processor and sound blaster 16 are used for experimental implementation, which executes A/D, D/A conversion and also is used as operating source of loudspeaker for audible noise cancellation.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.12
• /
• pp.117-126
• /
• 2005

In this paper, we present a new method for the reduction of the PAPR (peak to average power ratio) of OFDM signals. The idea behind the proposed method is that IFFT is implemented often with software for a digital signal processor such that we may avoid the repeated calculations to reduce the computational operations: we define sub-sequences in the IFFT process and then multiply the optimum phase rotation factors to them to minimize the PAPR. The PAPR reduction performance of the proposed method is equal to that of the interleaved partition scheme of the PTS (partial transmit sequence) method with only 1/3 computational operations of it.

• Journal of the Korea Convergence Society
• /
• v.8 no.7
• /
• pp.1-6
• /
• 2017

This paper presents the design of a frequency measurement device using ADC, EP2AGX FPGA and STM32 processor to accurately measure the frequency of a broadband high frequency signal. The ADC device used in this paper has a sampling frequency of 250 MSPS and a processing frequency bandwidth of 100 MHz. Due to its high sampling frequency, it is difficult to process in ordinary computers or processors, so we implemented the frequency measurement algorithm using the Altra EP2AGX FPGA. The measured frequency is sent to the direction detection controller in real time and fused with the phase signal to calculate the incident azimuth angle of the high frequency signal. The designed frequency measurement device is about 0.2 Mhz in frequency measurement error and 30% less than Anaren DFD-x, which is considered to contribute greatly to the design of radio monitoring and direction detection device.

• The Journal of Engineering Research
• /
• v.2 no.1
• /
• pp.39-47
• /
• 1997

This paper presents a single board digital signal processing system which can perform two-dimensional (2-D) digital infinite impulse response (IIR) filtering in realtime. We have developed an architecture to provide not only the necessary computational power but also a balance of the system input/output and computational requirements. The architecture achieves large system throughput by using highly parallel processing at both the system and processor levels. It reduces system data communication requirements significantly by taking advantage of a custom-designed processor and by providing each processor with its own input and ouput channel. After system initialization, almost 100 percent of the time is used for data processing. Data transfers occur concurrently with data processing. The functional level simulation reveals that the system throughput can reach as high as one pixel per system cycle. With only 10MHz clock frequency system, it can implement up to fourth order 2-D IIR filters for video-rate data ($512\times512$ pixels per frame at 30 frames per second). If we increase the system frequency, the system can be used for the preprocessing and postprocessing of video signal of HDTV.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.5
• /
• pp.34-41
• /
• 2011

This paper presents a 24 channel capacitive touch sensing ASIC. This ASIC consists of analog circuit part and digital circuit part. Analog circuits convert user screen touch into electrical signal and digital circuits represent this signal change as digital data. Digital circuit also has an I2C interface for operation parameter reconfiguration from host machine. This interface guarantees the stable operation of the ASIC even against wide operation condition change. This chip is implemented with 0.18 um CMOS process. Its area is about 3 $mm^2$ and power consumption is 5.3mW. A number of EDA tools from Cadence and Synopsys are used for chip design.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.6
• /
• pp.131-137
• /
• 2013

The barrel distortion makes serious problems in a wide-angle camera employing a lens of a short focal length. This paper presents a low-complexity hardware architecture for a real-time barrel distortion corrector and its implementation. In the proposed barrel distortion corrector, the conventional algorithm is modified so that the correction is performed incrementally, which results in the reduction of the number of required hardware modules for the distortion correction. The proposed barrel distortion corrector has a pipelined architecture so as to achieve a high-throughput correction. The correction rate is 74.86 frames per sec at the operating frequency of 314MHz in a $0.11{\mu}m$ CMOS process, where the frame size is $2048{\times}2048$. The proposed barrel distortion corrector is implemented with 14.3K logic gates.