• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1755-1764
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• 1997

In this paper, we proposed the mechanism for the buffer allocation and a cell scheduling method with logical separation a single buffer in the ATm switch, and analyzed the cell loss probability and the delay of each trafic (CBR/VBR/ABR) based on the weighted value and the dynamic cell service scheduling algorithm. The proposed switch buffering system classifies composite trafics incoming to the switch, according to the characteristic of traffic, then stores them in the logically separated buffers, and adopts the round-robin service with weighted value in order to transmit cells in buffers though one output port. We analyzed 4 cell service scheduling algorithms with dynamic round-robinfor each logically separated service line of a single buffer, in which buffers have the respective weighted values and 3 classes on mixed traffic which characteristized by traffic descriptor. In simulation, using SIMCRIPT II.5., we model the VBR and the ABR traffics as ON/OFF processes, and the CBR traffic as a Poisson processes. As the results of analysis according to the proposed buffer management mechanism and cell service algorithm, we have found that the required QoS of each VC can be quaranteed depends on a scale of weighted values allocated to buffers that changed the weighted values, and cell scheduling algorithm.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.429-438
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• 2001

GPS (Global Positioning System) is the most ideal navigation system which can be used on the earth irrespective of time and weather conditions. GPS has been used for various applications such as construction, survey, environment, communication, intelligent vehicles and airplanes and the needs of GPS are increasing in these days. This paper deals with the design and implementation of the RTOS (Real-Time Operating System) for a GPS navigation computer in the GPS/INS integrated navigation system. The RTOS provides the optimal environment for execution and the base platform to develop GPS application programs. The key facilities supplied by the RTOS developed in this paper are priority-based preemptive scheduling policy, dynamic memory management, intelligent interrupt handling, timers and IPC, etc. We also verify the correct operations of all application tasks of the GPS navigation computer on the RTOS and evaluate the performance by measuring the overhead of using the RTOS services.

• Proceedings of the Korea Society for Simulation Conference
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• 1992.10a
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• pp.3-3
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• 1992

컴퓨터 시스템의 개발 및 분석에 많이 활용되는 시뮬레이션 모델을 구축하는데 있어서 SIMSCRIT, GISS, SIMAN, SLA II등과 같은 시뮬레이션 전용언어가 많이 사용되지만, 이들은 새로운 전용언어의 습득, 시스템 프로그램과의 접속, 시뮬레이션 수행 속도면에서 부담을 주어왔다. 본 연구에서는 기존의 C언어 사용자들이 손쉽게 시뮬레이션 모델을 구축할 수 있도록 기존의 smpl을 확장하여 SMPLE(smpl extended)를 개발하였다. SMPLE의 모체의 smpl은 컴퓨터 시스템의 시뮬레이션 모델을 구현하기 위해 MIT에서 C언어를 이용하여 고안되었으며, C언어의 기능적인 확장으로서 라이브러리 함수들의 집합 형태를 갖는 시뮬레이션 서브 시스템이다. 이러한 라이브러리 함수들의 집합인 smpl 시뮬레이션 서브 시스템은 C언어 자체와 더불어 사건중심(event-oriented) 시뮬레이션 언어를 구성하며, smpl 시뮬레이터는 C 언어 프로그램으로 구현되다. smpl은 시뮬레이션하기 위한 설비(facility)들을 정의, 예약, 해제하거나 상태를 알아보는 함수를 제공하며, 시간의 관점에서 보면 토큰의 흐름은 일련의 대기시간과 활동시간에 의하여 나타낼 수 있게 된다. smpl은 사건의 스케쥴링(scheduling), 확률변수의 생성, 통계자료 수집 등에 관한 함수의 제공과, 시뮬레이션 시간의 전진과 사건발생의 순서를 조절해주는 기능을 제공한다. smpl 시뮬레이션 프로그램은 초기화루틴, 제어루틴 및 결과출력루틴으로 구성된다. 기존의 smpl에서 사용되는 프로그램의 자료구조(data structure)는 배열과 인덱스 구조가 사용되었다. 이러한 구조는 이미 완성되어 있는 프로그램 내에서는 효율성 면에서 좋겠지만, 변경이나 확장하기 위해 이 프로그램을 분석한다거나 필요한 기능을 추가하기 위해서는 매우 많은 어려움이 따르게 된다. 본 논문에서는 배열을 기반으로 하고 있는 smpl의 자료구조를 C의 structure와 pointer를 기반으로 하게끔 변경시키고 이에 따르는 제반 변경 사항을 수정 보완하여 프로그램의 분석을 용이하게 하며 기능의 변경 및 추가가 수월하게 하였고 메모리를 동적으로 관리할 수 있게 하였다. 또한 기존의 smpl에 디버깅용 함수 및 설비(facility) 제어용 함수를 추가하여 시뮬레이션 프로그램 작성을 용이하게 하였다. 예를 들면 who_server(), who_queue(), pop_Q(), push_Q(), pop_server(), push_server(), we(), wf(), printfct() 같은 함수들이다. 또한 동시에 발생되는 사건들의 순서를 조종하기 위해, 동시에 발생할 수 있는 각각의 사건에 우선순위를 두어 이 우선 순위에 의하여 사건 리스트(event list)에서 자동적으로 사건들의 순서가 결정되도록 확장하였으며, 설비 제어방식에 있어서도 FIFO, LIFO, 우선 순위 방식등을 선택할 수 있도록 확장하였다. SIMPLE는 자료구조 및 프로그램이 공개되어 있으므로 프로그래머가 원하는 기능을 쉽게 추가할 수 있는 장점도 있다. 아울러 SMPLE에서 새로이 추가된 자료구조와 함수 및 설비제어 방식등을 활용하여 실제 중형급 시스템에 대한 시뮬레이션 구현과 시스템 분석의 예를 보인다.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1318-1332
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• 1999

본 논문에서는 입출력 응용을 위해 collective I/O 기법을 기반으로 한 실행시간 시스템의 설계, 구현 그리고 그 성능평가를 기술한다. 여기서는 모든 프로세서가 동시에 I/O 요구에 따라 스케쥴링하며 I/O를 수행하는 collective I/O 방안과 프로세서들이 여러 그룹으로 묶이어, 다음 그룹이 데이터를 재배열하는 통신을 수행하는 동안 오직 한 그룹만이 동시에 I/O를 수행하는 pipelined collective I/O 등의 두 가지 설계방안을 살펴본다. Pipelined collective I/O의 전체 과정은 I/O 노드 충돌을 동적으로 줄이기 위해 파이프라인된다. 이상의 설계 부분에서는 동적으로 충돌 관리를 위한 지원을 제공한다. 본 논문에서는 다른 노드의 메모리 영역에 이미 존재하는 데이터를 재 사용하여 I/O 비용을 줄이기 위해 collective I/O 방안에서의 소프트웨어 캐슁 방안과 두 가지 모형에서의 chunking과 온라인 압축방안을 기술한다. 그리고 이상에서 기술한 방안들이 입출력을 위해 높은 성능을 보임을 기술하는데, 이 성능결과는 Intel Paragon과 ASCI/Red teraflops 기계 상에서 실험한 것이다. 그 결과 응용 레벨에서의 bandwidth는 peak point가 55%까지 측정되었다.Abstract In this paper we present the design, implementation and evaluation of a runtime system based on collective I/O techniques for irregular applications. We present two designs, namely, "Collective I/O" and "Pipelined Collective I/O". In the first scheme, all processors participate in the I/O simultaneously, making scheduling of I/O requests simpler but creating a possibility of contention at the I/O nodes. In the second approach, processors are grouped into several groups, so that only one group performs I/O simultaneously, while the next group performs communication to rearrange data, and this entire process is pipelined to reduce I/O node contention dynamically. In other words, the design provides support for dynamic contention management. Then we present a software caching method using collective I/O to reduce I/O cost by reusing data already present in the memory of other nodes. Finally, chunking and on-line compression mechanisms are included in both models. We demonstrate that we can obtain significantly high-performance for I/O above what has been possible so far. The performance results are presented on an Intel Paragon and on the ASCI/Red teraflops machine. Application level I/O bandwidth up to 55% of the peak is observed.he peak is observed.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.46 no.6
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• pp.503-512
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• 2018

SAR(Synthetic Aperture Radar) is a technology to acquire images by processing signals obtained from radar, and there is an increasing demand for utilization of high-resolution SAR images. In this paper, for high-speed processing of high-resolution SAR image data, a study for SAR image processing algorithms to achieve optimal performance in multi-core based computer architecture is performed. The performance deterioration due to a large amount of input/output data for high resolution images is reduced by maximizing the memory utilization, and the parallelization ratio of the code is increased by using dynamic scheduling and nested parallelism of OpenMP. As a result, not only the total computation time is reduced, but also the upper bound of parallel performance is increased and the actual parallel performance on a multi-core system with 10 cores is improved by more than 8 times. The result of this study is expected to be used effectively in the development of high-resolution SAR image processing software for multi-core systems with large memory.

• The KIPS Transactions:PartB
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• v.8B no.5
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• pp.523-532
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• 2001

A Critical issue in the performance of a video-on-demand system is the required I/O bandwidth of the Video server in order to satisfy clients requests, and it is the crucial resource that may cause delay increasingly. Several approaches such as batching and piggybacking are used to reduce the I/O demand on the video server through sharing. Bathing approach is to make single I/O request for storage server by grouping the requests for the same object. Piggybacking is th policy for altering display rates of requests in progress for the same object to merge their corresponding I/O streams into a single stream, and serve it as a group of merged requests. In this paper, we propose a reservation-based hybrid disk bandwidth reduction policy that dynamically reserves the I/O stream capacity of a video server for popular videos according to the loads of video server in order to schedule the requests for popular videos immediately. The performance of the proposed policy is evaluated through simulations, and is compared with that of bathing and piggybacking. As a result, we know that the reservation-based hybrid disk bandwidth reduction policy provides better probability of service, average waithing time and percentage of saving in frames than batching and piggybacking policy.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.5
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• pp.219-230
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• 2017

General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.