• Journal of the Institute of Convergence Signal Processing
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• v.1 no.2
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• pp.177-185
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• 2000

In this paper CPLD design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then each subround is executed using one clock. To improve clock frequency, online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. The cryptographic coprocessor is designed using Altera EPF10K100GC503-3 CPLD device and its operation is verified by encryption or decryption of text files through ISA bus interface. It consists of about 29,300 gates and performance of CPLD chip is about 44 Mbps encryption or decryption rate under 18 Mhz clock frequency and ECB mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.103-112
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• 2010

In this paper, we propose a coarse and fine frequency synchronization method which is suitable for the 3GPP(3rd Generation Partnership Project) LTE(Long Term Evolution) FDD(Frequency Division Duplexing) / TDD(Time Division Duplexing) dual mode system. In general, PSS(Primary Synchronization Signal) correlation based estimation method and CP(Cyclic Prefix) correlation based tracking loop are applied for coarse and fine frequency synchronization in 3GPP LTE OFDMA(Orthogonal Frequency Division Multiple Access) system, respectively. However, the conventional coarse frequency synchronization method has performance degradation caused by fading channel and squaring loss. Also, the conventional fine frequency synchronization method cannot guarantee stable operation in TDD mode because of signal power difference between uplink and downlink subframe. Therefore, in this paper, we propose enhanced coarse and fine frequency synchronization methods which can estimate more accurately in multi-path fading channel and high speed channel environments and has stable operation for TDD frame structure, respectively. By computer simulation, we show that the proposed methods outperform the conventional methods, and verify that the proposed frequency synchronization method can guarantee stable operation in 3GPP LTE FDD/TDD dual mode downlink receiver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.302-313
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• 2010

In this paper, we propose an enhanced AGC (Automatic Gain Control) structure and P-SCH detection method for initial cell search in 3GPP (3rdGenerationPartnershipProject) LTE (Long Term Evolution) FDD(Frequency Division Duplex) / TDD (Time Division Duplex) dual mode system. Since TDD frame structure consists of uplink subframe and downlink subframe, conventional AGC structure causes P-SCH detection performance degradation by increase of AGC variation due to signal power difference between uplink and downlink subframe. Also, P-SCH detection performance is degraded by distortion of P-SCH correlation characteristic in frequency offset and multipath fading channel environments. Therefore, we propose an AGC structure which can minimize P-SCH detection performance degradation with stable operation in 3GPP LTE TDD mode as well as FDD mode. Also we propose a P-SCH detection method which can reduce distortion of correlation chareteristics in frequency offset and multipath fading environments and obtain good P-SCH detection performance. Simulation results show that the proposed AGC structure and P-SCH detection method have stable AGC operation and excellent P-SCH detection performance for 3GPP LTE TDD / FDD dual mode downlink receiver in various channel environments.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.7
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• pp.28-34
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• 2011

Radiation characteristics of a dual-mode inductor loaded patch antenna using zeroth order resonance and half wavelength resonance are investigated. The isolation between two radiation patterns from the two different modes is improved by increasing the forward radiation and decreasing the horizontal radiation of half wavelength resonance mode. The frequency difference between the two resonant frequencies increases as the dielectric constant of the antenna substrate decreases and the operating frequency increases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.18-23
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• 2007

This paper presents a transmissive dispersion compensator based on tilted chirped fiber Bragg grating pairs which happen mode coupling between core mode and cladding mode. And, as a result of simulation, the phase matching condition and optimum tilted angle to maximize the mode-coupling in the dispersion compensator are shown and the dispersion slope and bandwidth in the proposed dispersion compensator is respectively 3,068ps/nm and 0.45nm.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.26-28
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• 2019

중요부하를 가지고 있는 계통연계 병렬인버터는 계통과의 연결이 끊길 경우 중요부하에 안정적인 전압공급을 위하여 끊김 없는 모드전환 동작이 요구된다. 기존 병렬인버터는 계통연계 시 전류제어모드 운전을 하고, 독립운전 시에는 전압제어모드 운전을 한다. 그래서 단독운전 발생 시 불안정한 전압을 부하에 공급하게 되고, 모드전환 시 제어기절체로 인해 인버터출력전압에 심각한 과도상태를 발생시켜 중요부하에 큰 손상을 입힐 수 있다. 본 논문에서는 Droop 제어 기반 계통연계 병렬인버터의 끊김 없는 모드전환 기법을 제안한다. 제안된 알고리즘은 1kW 시작품을 제작하여 타당성을 검증하였다.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.201-203
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• 2018

최근 휴대용 어댑터의 동향은 고주파수 전력 컨버터 설계를 통한 어댑터의 고효율화 및 소형화의 중요성을 강조하고 있다. 그러나 기존 준공진형(Quasi Resonant, QR) 플라이백 컨버터는 하드 스위칭 동작으로 고주파수 구동에 한계가 있으며, 누설 인덕턴스 에너지에 의한 손실로 인해 고효율을 달성하기가 어렵다. 반면, 능동 클램프 플라이백(Active Clamp Flyback, ACF) 컨버터는 ZVS(Zero Voltage Switching) 동작을 하여 고주파수 구동에 유리하고, 누설 인덕턴스 에너지를 입력으로 회기 시킴으로써 손실을 저감할 수 있다. 또한, 경계전류모드(Boundary Conduction Mode, BCM) 동작에서의 손실분석을 기반으로, 반도체 특성이 우수하여 고주파수 동작에 유리한 GaN-FET를 적용하고 최적 설계를 진행함으로써 고효율 및 고전력밀도를 달성하였다. 따라서 본 논문에서는 GaN-FET를 기반으로 하는 고효율 및 고전력밀도 BCM ACF 컨버터의 최적 설계 방안을 제시하고 65W급 시작품의 실험결과를 통해 이를 검증한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.404-407
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• 2011

This paper presents a design of current mode PWM/PFM DC-DC Boost converter. This DC-DC Boost Converter operates with PWM mode at the heavy loads and with PFM mode at light loads. The DC-DC boost converter is designed with CMOS 0.35${\mu}m$ technology. It operates at 500KHz and can drive a load current up to 600mA. It has a maximum power efficiency of 92.1%. The total chip area is $1300{\mu}m{\times}1070{\mu}m$ including pads. The DC-DC boost converter operates in a wide range of load currents while occupying a small chip area.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1143-1150
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.12
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• pp.1447-1453
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• 2010

In this paper, the design and the fabrication of dual-band bandpass filter using two dual-mode resonators is presented. Dual-mode resonator using a short stub is miniaturized by inter-digital capacitor and stepped impedance. Two dual mode resonators are designed to have different resonant frequencies, one for the lower passband and the other for the upper passband. Transmission zero is positioned at low or high rejection bands with a sharp skirt characteristic. Dual-band operation can be achieved using dual feeding structure. For WLAN, the proposed filter at 2.45/5.25 GHz is designed and fabricated. The size of the filter is as compact as 1$10.83\;mm{\times}5.3\;mm$.