• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.3
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• pp.39-49
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• 2003

The delta operator approach and the singular perturbation technique are introduced. The former reduces the round-off error in the numerical computation. The latter reduces computing time by decoupling the original system into the fast and slow sub-systems. The aircraft dynamics consists of the Phugoid and short-period motions whether its model is longitudinal or lateral. In this paper, an approximated solutions of lateral dynamic model of Beaver obtained by using those two methods in compared with the exact solution. For open-loop system and closed-loop system, and approximated solution gets identical to the exact solution with only one iteration and without iteration, respectively. Therefore, it is shown that implementing those approaches is very effective in the flight dynamic and control.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1B
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• pp.1-7
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• 2010

In this paper, a high-performance fault-tolerant switching network using a deflection self-routing was proposed. From an abstract algebraic analysis of the topological properties of the Delta network, which is a baseline switching network, we derive the Multidimensional Ring-Delta network: a multipath switching network using a deflection self-routing algorithm. All of the links including already existing links of the Delta network are used to provide the alternate paths detouring faulty/congested links. We ran a simulation analysis under the traffic loads having the non-uniform address distributions that are usual in Internet. The throughput of $1024\;{\times}\;1024$ switching network proposed is better than that of the 2D ring-Banyan network by 13.3 %, when the input traffic load is 1.0 and the hot ratio is 0.9. The reliability of $64\;{\times}\;64$ switching network proposed is better than that of the 2D ring-Banyan network by 46.6%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.1
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• pp.9-15
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• 2015

A CMOS band-pass delta-sigma modulator(BPDSM) and cascode class-E power amplifier have been developed CMOS for Class-S power amplifier applications. The BPDSM is operating at 1-GHz sampling frequency, which converts a 250-MHz sinusoidal signal to a pulse-width modulated digital signal without the quantization noise. The BPDSM shows a 25-dB SQNR(Signal to Quantization Noise Ratio) and consumes a power of 24 mW at an 1.2-V supply voltage. The class-E power amplifier exhibits an 18.1 dBm of the maximum output power with a 25% drain efficiency at a 3.3-V supply voltage. The BPDSM and class-E PA were fabricated in the Dongbu's 110-nm CMOS process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1800-1805
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• 2008

Shiro-abhyanga is one of treatments of Ayurveda, which is the ancient system of health care and medicine in India. In this essay, I examined the effect of Shiro-abhyanga for relaxing stress of women in twentieth by the means of the brain wave test. The brain wave test showed that Shiro-abhyanga reduced Delta and Theta waves of the left brain but increased $\alpha$, SMR, Low-$\beta$ waves of the right brain. Delta and Theta waves are usually found in sleeping time. Their high measurement in awakening instructs the stress and depressing situations of objects. However the treatment of Shiro-abhyanga made the decrease of Delta and Theta waves and the increase of Alpha wave in working time. Alpha wave appears while objects are comfortable and peaceful from the relaxation of body and mind. Therefore the growth of Alpha wave says that the treatment of Shiro-abhyanga has an effect on mitigation of stress.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of KIISE
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• v.42 no.9
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• pp.1078-1089
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• 2015

In this paper, we propose the Min-hash Assisted Delta-compression Engine(MADE) to improve the lifetime of NAND flash-based storages at the device level. MADE effectively reduces the write traffic to NAND flash through the use of a novel delta compression scheme. The delta compression performance was optimized by introducing min-hash based LSH(Locality Sensitive Hash) and efficiently combining it with our delta compression method. We also developed a delta encoding technique that has functionality equivalent to deduplication and lossless compression. The results of our experiment show that MADE reduces the amount of data written on NAND flash by up to 90%, which is better than a simple combination of deduplication and lossless compression schemes by 12% on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.50-59
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• 2007

[ $0.18-{\mu}m$ ] CMOS 1.2-V 2nd-order ${\Sigma}{\Delta}$ modulator with full-feedforward topology is designed. Using full-feedforward topology makes op-amp performance requirements much less stringent, therefore it has been adopted as a good candidate for low-voltage low-power applications throughout the world. Also, ${\Sigma}{\Delta}$ modulator is designed with top-down design approach, therefore various nonideal effects of op-amp are modeled in this paper.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.123-124
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• 2008

본 논문에서 설계한 온도센서는 $0.l8{\mu}m$ CMOS 공정으로 $-55^{\circ}C{\sim}125^{\circ}C$의 온도 범위에서 ${\pm}0.1^{\circ}C$의 정확도를 갖는다. 이 센서는 parasitic PNP 트랜지스터로 온도 변화에 따른 전압을 추출하고 시그마-델타 변조기를 이용하여 디지털 온도 값을 얻기 위한 비트스트림을 생성한다. 또한, 이상적이지 않은 요소로 인해 발생할 수 있는 에러를 $0.01^{\circ}C$ 레벨로 감소시키기 위해 DEM(Dynamic Element Matching)과 2차 시그마-델타 변조기를 이용하였고, Bandgap Reference 회로로 온도 변화에 상관없이 일정한 bias 전압을 생성한다. 설계된 온도센서의 면적은 PAD를 포함하여 $0.98mm{\times}0.92mm$이고, 1.8V 단일 전원에서 동작한다.

• Ecology and Resilient Infrastructure
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• v.4 no.4
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• pp.245-254
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• 2017

In this study, the flow characteristics and bed changes in the upstream and downstream of weirs with the variation of the weir angels are investigated quantitatively through the laboratory experiments. As the angle of weir increases, the effective weir length decreases. Delta is developed by the sediments inflow upstream and migrates downstream. Delta migration speed decreases as it approaches to the weir upstream, and the size is getting big. As the dimensionless weir length increases, the dimensionless wave length decreases at the downstream of the weir. However, the dimensionless bar height decreases. The dimensionless wavelength increases with the bar height downstream from the weir.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.5
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• pp.193-197
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• 2017

In this paper, we present a low-power delta-sigma based digital frequency synthesizer with high frequency resolution for bio sensor networks. Biomedical radio-frequency (RF) transceivers require miniaturized forms with a long battery life and low power consumption. For the technology scaling, digital circuits have become preferable compared to analog circuits because of the aggressive cost, size, flexibility, and repeatability. Therefore, the digital circuits based on standard-cell library are used to reduce a power consumption. Additionally, a delta-sigma is used for making fractional frequency tuning range. From the simulation, we confirmed that proposed scheme has good performance in accordance with power and frequency resolution.