• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.322-329
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• 2007

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has been designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.330-336
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• 2007

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has tern designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.4
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• pp.121-127
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• 2024

In this paper, FEM (Front-End Module) MMIC, a key component for the application of the satellite communication terminal transmission and reception module of the multi-phase array structure, was designed and verified as a single chip by designing the Power Amplifier (PA) and the Low Noise Amplifier (LNA). It was manufactured using the GaAs PP10 (100nm) process, a compound semiconductor process from Win-semiconductors, and the operating frequency band of 7.2-10.5GHz operation, output 1W, and noise index of 1.5dB or less were secured using a dedicated test board. The developed FEM MMIC can be used as a single chip, and the components PA and LNA can also be used as each device. The developed device will be used in various applications of Minsu/Gunsu using the X band and the localization of overseas parts.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.111-116
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• 2003

In this paper, a CMOS baseband analog receiver for wireless home network is discussed. It is composed of a Gilbert type mixer, an Elliptic 6th order 1ow pass filter, and a 6-bit A/D converter. The main role of the mixer is generating a mixed analog signal between the 200MHz output signal of CMOS RF stage and the 199MHz local oscillator. After the undesired high frequency component of the mixed signal comes out. Finally, the analog signal is converted into digital code at the 6-bit A/D converter, The proposed receiver is fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly 5-metal CMOS technology, and the chip area is 200${\mu}{\textrm}{m}$ X1400${\mu}{\textrm}{m}$. the receiver consumes 130㎽ at 2.5V power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1084-1090
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• 2009

This paper presents a balun consisting of a T-junction, a Right/Left Handed Transmission line(RLH-TL), and a conventional Right Handed(RH) line. It is assumed that the RLH-TL consists of N unit-cells. We provide closed-form solutions and design a very compact wideband(80 %) balun using CPW lines based on the obtained solutions. Then, we propose a capacitively loaded loop antenna designed for a uniform current distribution. The antenna resistance of the proposed antenna at resonance is about 204 ohms. The length of the unit cell is about $\lambda/12$(total length: $1\;\lambda$). The magnetic field generated from the proposed antenna is stronger than that of the conventional one by as much as 20 dB. We used a coplanar strip line(CPS) to combine the loop antenna and balun. The proposed antenna may be used as a near field UHF RFID reader antenna.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.5
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• pp.538-544
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• 2011

This paper presents a compact single balanced diode mixer fabricated using a 0.1 ${\mu}M$ GaAs p-HEMT commercial process for an E-band frequency up/down converter. This mixer includes a LO balun employing a Marchand balun with a good RF performance. In order to improve the port-to-port isolation, a high pass filter and a low pass filter are include in this mixer at the RF and IF ports, respectively. The fabricated mixer with a very compact size of 0.58 mm2(0.85 mm${\times}$0.68 mm) exhibits a conversion loss of 8～12 dB and an input P1dB of 1～5 dBm at the LO power of 10 dBm from 71～86 GHz.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.4.2-4.2
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• 2009

10년 후면 영어와 한국어가 실시간으로 자동 통역되는 통역기가등장하며, 컴퓨터의 키보드 나 마우스 등은 음성으로 대체되며, 인간과대화를 나누는 로봇이 등장하여 대부분의 인간 허드렛일을 대행 할 것으로 예상된다. 이러한 인공 지능형기기를 구현하기 위해서는 현재보다 1천배 이상의 성능을 보이는 즉, 테라급의 CPU와 메모리가 필요하다. 현재 반도체소자의 주류를 이루고 있는실리콘 트랜지스터는 무어 법칙에 따라 매18개월마다 2 배씩트랜지스터 집적도가 증가되어 왔으며 현재 32nm가 시장 출시를 앞두고 있으나 2016년 이후 22nm 이하는 특성 불균일/열 발생 과 같은 기술적 한계와 천문학적으로 늘어나는 칩 제조비용 때문에 제품 출시가 매우 어려울 것으로 여겨진다. 교육과학기술부는 이러한 한계 극복을 위해 21세기 Frontier 프로그램으로 테라급나노소자개발사업단을 2000년 7월 발족 하였으며 본 사업단은 테라급의 성능과 메모리 집적도를 갖는 나노소자개발을 최종목표로 출범 하였다. 프론티어사업은 10년 이상의 장기적인 개발기간이 필요한 'High Risk, High Return'의 특성을 갖고 있다. 본사업단은 이러한 프론티어사업의 취지에 따라 철저한 사전기획과 기술 환경변화에 따른 신속한 대응력, 철저한현장 중심적 사업관리를 해왔다. 본 재료학회 추계학술대회에서는 본 사업단이 이룩한 성과와 미래의 나노소자들을 소개할 예정이다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.36-43
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• 1999

A new design of a Direct Digital Frequency Synthesizer(DDFS) is presented, where a pipelined Coordinate Rotate Digital Computer(CORDIC) circuit is employed to calculate amplitude values of all the phase angles of sinusoidal waveforms produced. a near-optimal number of pipeline stages is determined based on an error analysis of calculated amplitude values in terms of the number of bits. The DDFS was implemented using a field programmable gate array, yielding a stable operating frequency of 11.75MHz. The measurement results show higher resolution, faster operating speed and simpler fabrication process, compared to ROM-based counterparts. The CORDIC-based DDFS yields 5 times higher resolution than conventional ROM-based versions.