• Korean Journal of Crystallography
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• v.12 no.2
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• pp.102-112
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• 2001

The mechanical properties of silicon crystals are important from the viewpoint of wafer and device fabrication processes. It is now widely recognized that silicon undergoes a series of phase transformations when subjected to high pressures, using conventional high pressure devices, such as diamond anvils or indenters. Diamond tip scratching on a silicon surface in the various conditions introduces various kinds of mechanical damage and stressed states. Micro Raman spectroscopy was used to observe the phase transition of single crystal silicon. As results, different morphologies were observed as functions of scratching speed and loading condition and various phases were observed as functions of scratching speed and loading condition.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.5
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• pp.179-184
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• 2018

To lessen oxygen concentrations in a wafer through modifying the length of graphite heaters, we investigated the influence of relative distance from heater to quartz crucible on temperature profile of hot-zone in Czochralski silicon-crystal growth by simulation. In particular, ATC temperature and power profiles as a function of different ingot body positions were investigated for five different heater designs; (a) typical side heater (SH), (b) short side heater-up (SSH-up), (c) short side heater-low (SSH-low), (d) bottom heater without side heater (Only-BH), and (e) side heater with bottom heater (SH + BH). It was confirmed that lower short side heater exhibited the highest ATC temperature, which was attributed to the longest distance from triple point to heater center. In addition, for the viewpoint of energy efficiency, it was observed that the typical side heater showed the lowest power because it heated more area of quartz crucible than that of others. This result provides the possibility to predict the feed-forward delta temperature profile as a function of various heater designs.

• Korean Chemical Engineering Research
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• v.58 no.3
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• pp.369-380
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• 2020

Most mono-crystalline silicon ingots are manufactured by the Czochralski (Cz) process. But If there are oxygen impurities, These Si-ingot tends to show low-efficiency when it is processed to be solar cell substrate. For making single-crystal Si- ingot, We need Czochralski (Cz) process which melts molten Si and then crystallizing it with seed of single-crystal Si. For melts poly Si-chunk and forming of single-crystalline Si-ingot, the heat transfer plays a main role in the structure of Cz-process. In this study to obtain high-quality Si ingot, the Cz-process was modified with the process design. The crystal growth simulation was employed with pulling rate and rotation speed optimization. Studies for modified Cz-process and the corresponding results have been discussed. The results revealed that using crystal growth simulation, we optimized the oxygen concentration of single crystal silicon by the optimal design of the pulling rate, rotation speed and melt charge level of Cz-process.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.48.1-48.1
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• 2010

Mono-crystalline silicon solar cell is fabricated by using alkali metals. These alkali metal, used in wet etching process, must be removed for the high efficiency solar cell. As wet etching process has been adapted due to its low cost. But lots of alkali metals like potassium remains on the silicon surface and acts as impurities. To remove these alkali metals many of cleaning process have to be applied when solar cell manufacturing process. In terms of alkali metal removal, modified etchant solution is required for concise cleaning process. In this paper ethylenediamine was used and proposed for the substituion of postassium hydroxide.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.249-255
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• 2002

For a formation of membrane structures, single crystal silicon wafers have been anisotropically etched with solutions of KOH and KOH-IPA. The etching rate was observed to be strongly dependent upon the etchant temperature and concentration. Mask patterns for the etching experiment was aligned to incline $45^{\circ}$on the primary flat of the silicon wafer. The different etching characteristics were observed according to pattern directions and etchant concentration. When the KOH concentration was fixed to 20 wt%, the U-groove etching shape was observed for the etching temperature of above $80^{\circ}C$, and V-groove shapes observed at below $80^{\circ}C$. Hillocks, which were generated at the etched silicon surfaces, has been decreased as the increasing of the etchant temperature and concentration.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.23-25
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• 2003

단결정 실리콘의 이방성 습식식각을 위하여 KOH 용액을 사용하여 식각 특성을 관찰하였다. 식각율은 식각액의 온도와 농도에 따라 변하는 것이 관찰되었으며, 패턴 형성 방향과 식각액의 농도에 따라 식각 형태가 다름도 알 수 있었다. 식각용액의 농도 20wt0% 이고 식각 시의 온도가 $80^{\circ}C$ 이상에서는 알파벳 "U" 자 모양의 형태로 식각이 이루어지고, 그 이하의 온도와 농도에서는 "V" 자 모양의 식각형태가 이루어졌다.; 자 모양의 식각형태가 이루어졌다.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.47.2-47.2
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• 2010

For reducing outer reflection in mono-crystalline silicon solar cell, wet texturing process has been adapted for long period of time. Nowadays mixed solution with potassium hydroxide and isopropyl alcohol is used in silicon surface texturing by most manufacturers. In the process of silicon texturing, etch rate is very critical for effective texturing. Several parameters influence the result of texturing. Most of all, temperature, process time and concentration of potassium hydroxide can be classified as important factors. In this paper, temperature, process time and concentration of potassium hydroxide were set as major parameters and 3-level test matrix was created by using robust design for the optimized condition. The process optimization in terms of lowest reflection and stable etch rate can be traced by using robust design method.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.109-109
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• 2011

1T-1C로 구성되는 기존의 DRAM(Dynamic Random Access Memory)은 데이터를 저장하기 위한 적절한 capacitance를 확보해야 한다. 따라서 캐패시터 면적으로 인한 집적도에 한계에 직면해있다. 따라서 이를 대체하기 위한 새로운 DRAM인 1T (Transistor) DRAM이 각광받고 있다. 기존의 DRAM과 달리 SOI (Silicon On Insulator)기술을 이용한 1T-DRAM은 데이터 저장을 위한 캐패시터가 필요없다. Impact Ionization 또는 GIDL을 이용해 발생한 정공을 채널영역에 가둠으로 서 발생하는 포텐셜 변화를 이용한다. 이로서 드레인 전류가 변화하며, 이를 이용해 '0'과 '1'을 구분한다. 기존의 1T-DRAM은 단결정 실리콘을 이용하여 개발되었으나 좀더 광범위한 디바이스로의 적용을 위해서는 다결정 실리콘 박막의 형태로 제작이 필수적이다. 단결정 실리콘을 이용할 경우 3차원 집적이나 기판재료선택에 제한적이지만 다결정 실리콘을 이용할 경우, 기판결정이 자유로우며 실리콘 박막이나 매몰 산화층의 형성 및 두께 조절이 용이하다. 때문에 3차원 적층에 유리하여 다결정 실리콘 박막 형태의 1T-DRAM 제작이 요구되고 있다. 따라서 이번연구에서는 엑시머 레이저 어닐링 및 고상결정화 방법을 이용하여 결정화 시킨 다결정 실리콘을 이용하여 1T-DRAM을 제작하였으며 메모리 특성을 확인하였다. 기판은 상부실리콘 100 nm, buried oxide 200 nm로 구성된 SOI구조의 기판을 사용하였다. 엑시머 레이저 어닐링의 경우 400 mJ/cm2의 에너지를 가지는 KrF 248 nm 엑시머 레이저 이용하여 결정화시켰으며, 고상결정화 방법은 $400^{\circ}C$ 질소 분위기에서 24시간 열처리하여 결정화 시켰다. 두가지 결정화 방법을 사용하여 제작되어진 박막트랜지스터 1T-DRAM 모두 kink 현상을 확인할 수 있었으며 메모리 특성 역시 확인할 수 있었다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.20.2-20.2
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• 2009

최근 무전해 식각법을 이용한 실리콘 나노와이어 합성이 다양한 각도에서 이루어지고 있다. 무전해 식각법을 통한 나노와이어 합성은, 단결정 실리콘 기판에 촉매를 올려 기판을 식각할 수 있는데, 이 방법을 이용하여 넓은 면적의 수직방향으로 배열된 10 ~ 300nm 지름의 단결정 실리콘 나노와이어를 합성할 수 있다. 본 연구에서는 무전해 식각법으로 boron이 도핑된 p-type실리콘 기판을 식각하여 실리콘 나노와이어를 합성하였고, 단일 나노와이어의 field-effect transistor(FET) 소자가 가지는 전기적 특성에 대하여 분석하였다. 특히 무전해 식각법을 이용하여 나노와이어를 합성할 때, 촉매로 사용되는 Ag particle이 나노와이어에 미치는 영향에 대해서 분석해 보았다. FET 소자의 게이트 절연막은 가장 일반적으로 사용되는 SiO2 (300nm)와 고유전체로 잘 알려진HfO2(80nm)를 사용하여 전기적 특성을 비교하여 보았다. 한편, HfO2 박막은 atomiclayer deposition(ALD)장비를 이용하여 증착하였다. 합성된 실리콘 나노와이어의 경우 X-ray diffraction(XRD)로 결정성을 확인하였으며, high-resolution transmission electron microscopy(HRTEM)으로 결정성 및 나노와이어의 표면 형태를 확인하였다. 전기적 특성은 I-V 측정을 통하여 Ion/Ioff ratio, 이동도, subthreshold swing, subthreshold voltage값을 평가하였다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.3
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• pp.449-455
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• 1997

The anisotropic etching behavior of single crystal silicon were studied in aqueous KOH solution. N-type (100) oriented single crystal silicon wafers were used for the study, and the $SiO_2$ layer, whose etching rate is known to be much slower than that of silicon in the KOH solution, was used as a mask for the silicon etching. The silicon etching rate and the etching properties are shown to be a function of etchant temperature uniformity, circulation speed, and circulation direction of the etchant as well as the etchant concentration and the temperature. The etching rate is increased as the temperature is increased from $10\mu \textrm{m}/hr$ to $250\mu \textrm{m}/hr$ in the range of $50^{\circ}C~105^{\circ}C$. Hillock density and height is observed to be correlated with the etchant concentration and the etch temperature. The variation of the hillock density was explained by the ratio between the etching rate of (100) orientation and that of (111) orientation.