• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.111-119
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• 1997

This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently used in constructing the digital logic systems based on the graph theory. And we discussed the function minimization method of the n-variables multiple-valued functions. The proposed method has the visible, schematical and regular properties.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.22-32
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• 2004

In this paper, we proposed MOVAG(Multi Output Value Array Graphs) based on OVAG by Honghai Jiang to construct multiple valued logic function The MDD(Muliple-valued Decision Diagra) needs many processing time and efforts in circuit design for given multi-variable function by D.M.Miller, and we designed a MOVAG which has reduce the data processing time and low complexity. We propose the construction algorithm and input matrix selection algorithm and we designed the multiple-valued logic circuit using T-gate and verified by simulation results.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1851-1864
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• 1997

This paper presents an algorithm simplifying the ESOP function by several rules. The algorithm is repeatedly performing operations based on the state of each terms by the product transformation operation of two functions and thus it is simplifying the ESOP function through the reduction of the product terms. Through the minimization of the product terms of the multi-valued input binary multi-output function, an optimization of the input has been done using EXOR PLA with input decoder. The algorithm when applied to four valued arithmetic circuit has been used for a EXOR logic circuit design and the two bits input decoder has been used for a EXOR-PLA design. It has been found from a computer simulation(IBM PC486) that the suggested algorithm can reduce the product terms of the output function remarkably regardless of the number of input variables when the variable AND-EXOR PLA is applied to the poperation circuit.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1995.10a
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• pp.1087-1090
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• 1995

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.29-33
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• 1978

In this paper, the properties of Galois fields defined over any finite field are analysed to derive Galois switching functions and the arithmetic operation methods over any finite field are showed. The polynomial expansions over finite fields by Lagrange's interpolation method are derived and proved. The results are applied to multivalued single variable logic networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.411-421
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• 1988

This paper offers a method to design CCD four-valued circuits using the tabular method. First, the four-valued logic function is decomposed by hand-calculation or computer program. Nest, the algorithm is derived form the tabular method based on the decomposition process to realize the DDC four-valued circuit. According to this algorithm, the two-variable four valued logic function is decomposed and realized by CCD network with four basic gates. The synthesis method in this paper proves that the number of devices and cost is considerably reduces as compared with the existing methods to realize the same logic functions.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.587-592
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• 2002

본 논문에서는 De Bruijn 그래프에 기초한 다중처리기구성의 한 가지 방법을 제안하였다. 제안한 방법에서는 유한체상의 수학적 성질과 그래프의 성질을 사용하여 변환연산자를 제한하였으며, 이들 변환연산자를 이용하여 De Bruijn 그래프의 변환표를 도출하였다. 그리고, 이 변환표로부터 유한체상의 De Bruijn 그래프를 도출하였다. 제안한 다중처리기는 유한체상의 임의의 소수와 양의 정수에 대해 구성할 수 있으며 고장허용컴퓨팅시스템, 파이프라인 시스템, 병렬처리 네트워크, 스위칭 함수와 이의 회로, 차세대 디지털논리시스템 및 컴퓨터구조 중의 하나인 다치디지털논리시스템 등에 적용할 수 있으리라 전망된다.

• Journal of Advanced Navigation Technology
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• v.16 no.1
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• pp.62-69
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• 2012

Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.4
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• pp.285-301
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• 1988

The symbol error rate equations of multi-level quadrature PRS(QPRS) system have been derived in the individual and composite environment of Gaussian/impulsive noise, cochannel CW interference, carrier offset, phase jitter and fading. And using the derived error rate equations, the probability of error has been evaluated and shown in graphs as functions of carrier to noise power ratio, carrier to interference power ratio, phase error, impulsive index, the ration of Gaussian noise to impulsive noise power component, signal to noise power ration in phase locked loop(PLL), and fading figures. The rseults show that the error rate performances are generally more more degraded by impulsive noise than by Gaussian noise. But on the contrary the erors occurred more frequently by Gaussian noise than impulsive noise in a fading environment.