• Journal of KIISE:Computer Systems and Theory
• /
• v.33 no.5
• /
• pp.297-305
• /
• 2006

Trace-driven simulation is widely used for measuring the performance of a microprocessor in its initial design phase. However, since it requires much time and disk space, the statistical simulation has been studied as an alternative method. In this paper, statistical simulations are performed for a high performance superscalar microprocessor with a perceptron-based multiple branch predictor. For the verification, various hardware configurations are simulated using SPEC2000 benchmarks programs as input. As a result, we show that the statistical simulation is quite accurate and time saving for the evaluation of microprocessor architectures with multiple branch prediction.

• Proceedings of the Korean Information Science Society Conference
• /
• 2001.10c
• /
• pp.13-15
• /
• 2001

최근에 이르러 프로세서의 병렬성을 분석적 기법으로 예측하기 위한 연구가 활발해지면서 프로세서의 성능 예측 모델에 대한중요성이 대두되고 있다. 그러나 기존의 연구는 현재 광범위하게 사용되고 있는 다중 분기 예측법을 이용하는 프로세서에 대하여 분기 차수와 관계없는 재귀적 성능 모델을 제공해주지 않는다. 본 논문에서는 이것을 해결하기 위하여, 매 싸이클마다 명령어 종속 트리를 구성하고 종속인 명령어 간에 상대적인 병렬도 갓을 부여하여 성능 예측 모델 입력 데이타를 측정하였다. 그 곁과, 다중 분기 예측법을 사용하는 프로세서에서 정수형 프로그램에 대한 성능을 기존의 성능모델보다 작은 상대 오차로 예측할 수 있다.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.803-804
• /
• 2006

This paper presents a multiple branch predictor with perceptrons. We describe our design and evaluate it with the SPEC 2000 benchmarks. Our predictor achieves increased accuracy than the previous multiple branch predictors.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.3
• /
• pp.621-626
• /
• 2009

This paper presents a multiple branch predictor using perceptrons. The key idea is to apply neural networks to the multiple branch predictor. We describe our design and evaluate it with the SPEC 2000 integer benchmarks. Our predictor achieves increased accuracy than the Bi-Mode and the YAGS multiple branch predictor with the same hardware cost.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.7
• /
• pp.1443-1449
• /
• 2009

This paper presents a profiling model of a wide-window superscalar microprocessor using multiple branch prediction. The key idea is to apply statistical profiling technique to the superscalar microprocessor with a wide instruction window and a multiple branch predictor. The statistical profiling data are used to obtain a synthetical instruction trace, and the consecutive multiple branch prediction rates are utilized for running trace-driven simulation on the synthesized instruction trace. We describe our design and evaluate it with the SPEC 2000 integer benchmarks. Our performance model can achieve accuracy of 8.5 % on the average.