• Proceedings of the Korean Magnestics Society Conference
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• 2012.05a
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• pp.131-132
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• 2012

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2291-2293
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• 2011

In this paper, the composes with digital position with a computer logical operation order with the signal processing method which is pliability and result of the logical operation which confronts in input signal from the outside input-output Channel leads and about the drive which the possibility to output at the outside is a research. This Decoder IC Multiplexer & De-multiplexer, position the function with from the digital signal circle where the imagination embodiments and BIT outputs of IC etc. are possible is possible in basic and usefully from the general industrial, could be used.

• 전기의세계
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• v.39 no.12
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• pp.12-20
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• 1990

기존의 이진논리는 애매모호한 인간의 지식을 표현하는데 많은 여러움이 있었다. 컴퓨터의 사고를 보다 인간에 가깝게 하기 위해 0과 1의 이진논리가 아닌, 0과1 사이의 실수로 애매모호함을 표현하는 Zadeh의 퍼지집합이론이 제안되었다. 이를 기초로 하여, 실제로 여러 종류의 퍼지 연산들을 수행하는 퍼지프로세서들이 개발되었으며, 퍼지 컴퓨터를 실현시키기 위한 연구가 활발히 진행되고 있다. 본고에서는 퍼지논리에 기초하여 퍼지정보처리(Fuzzy Information Processing)을 수행하는 대표적인 하드웨어 시스템인 퍼지 컴퓨터와 퍼지 컨트롤러 (fuzzy controller)에 대해 알아보고 다단계 퍼지 추론을 수행하는 퍼지 메모리 모듈(fuzzy memory module)의 기본인 퍼지 플립플롭에 대해 알아보고자 한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.189-194
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• 2017

The reversibility of a quantum logic circuit can be realized when two reversible conditions of information reversible and energy reversible circuits are satisfied. In this paper, we have modeled the computation cycle required to recover the information reversibility from the multivalued quantum logic to the original state. For modeling, we used a function embedding method that uses a unitary switch as an arithmetic exponentiation switch. In the quantum logic circuit, if the adjoint gate pair is symmetric, the unitary switch function shows the balance function characteristic, and it takes 1 cycle operation to recover the original information reversibility. Conversely, if it is an asymmetric structure, it takes two cycle operations by the constant function. In this paper, we show that the problem of 2-cycle restoration according to the asymmetric structure when the hybrid MCT gate is realized with the ternary M-S gate can be solved by equivalent conversion of the asymmetric gate to the gate of the symmetric structure.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1995.10a
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• pp.1091-1094
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• 1995

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.35-43
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• 2008

A new effective parallel decoding method has been developed for context-based adaptive variable length codes. In this paper, several new design ideas have been devised for scalable parallel processing, less area, and less power. First, simplified logical operations instead of memory look-ups are used for fast low power operations. Second the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of input are simultaneously analyzed. For comparison, we have designed the logical operation based parallel decoder for M=8 and a typical conventional method based decoder. High speed parallel decoding is possible with our method. For similar decoding rates (1.57codes/cycle for M=8), our new approach uses 46% less area than the typical conventional method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.552-554
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• 2015

본 논문은 AVX2 (Advanced Vector eXtension 2) 명령어 집합을 이용하여 HEVC (High Efficiency Video Coding) 복호화기의 역-변환 모듈을 고속화하는 방법을 제안한다. AVX2 명령어 집합은 256 비트 레지스터를 사용하여 다수의 데이터를 한번의 명령을 통해 병렬적으로 연산할 수 있으며 반복적인 산술 연산 혹은 논리 연산 구조에서 효율적이다. 제안하는 방법은 AVX2 명령어 집합을 이용하여 $8{\times}8{\sim}32{\times}32$ 크기의 TU (Transform Unit) 단위로 수행되는 역-변환 연산을 행렬의 곱 형태로 연산하여 고속화하였다. 실험 결과 AVX2 명령어 집합을 이용한 역-변환 연산은 Chen 알고리즘에 비해 평균 51% 속도 향상을 보였으며 SSE (Streaming SIMD Extension) 명령어 집합을 이용한 연산에 비해 평균 20%의 속도 향상 결과를 얻을 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.880-883
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• 2005

This paper presents a method of constructing the sequential logic machines over finite fields(or galois fields). The proposed the sequential logic machines is constructed by as following. First of all, we obtain the linear characteristics between present state and next state based on mathematical properties of finite fields and sequential logic machines. Next, we realize the sequential logic machines over finite field GF(P) using above linear characteristics and characteristic polynomial that expressed using by matrix.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1079-1085
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• 2013

Due to the limited power supply resources, it is essential that the minimization of algorithmic operation and the reduction of the hardware logical-resources in the design of the satellite transponder. It is also required that the transponder process the signals of various bandwidth efficiently, that is suitble for the SDR-based implementation. This paper proposes a variable rate down sampler which can provide variable bandwidth and data rate for carrier, ranging and sub-band command signals respectively. The proposed down sampler can provide multiple $2^M$ decimated outputs from a single half band filter with recursive arithmetic architecture, which can minimize the hardware resources as well as the arithmetic operations. The algorithm for hardware implementation as well as the analysis for the passband flatness and aliasing is presented and varified by the FPGA implementation.