• Korean Journal of Logic
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• v.8 no.2
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• pp.3-32
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• 2005

Hilbert's rational ambition to establish consistency in Number theory and mathematics in general was frustrated by the fact that the statement itself claiming consistency is undecidable within its formal system by $G\ddot{o}del's$ second theorem. Hilbert's optimism that a mathematician should not say "Ignorabimus" ("We don't know") in any mathematical problem also collapses, due to the presence of a undecidable statement that is neither provable nor refutable. The failure of his program receives more shock, because his system excludes any ambiguity and is based on only mechanical operations concerning signs and strings of signs. Above all, $G\ddot{o}del's$ theorem demonstrates the limits of formalization. Now, the notion of provability in the dimension of syntax comes to have priority over that of semantic truth in mathematics. In spite of his failure, the notion of algorithm(mechanical processe) made a direct contribution to the emergence of programming languages. Consequently, we believe that his program is failure, but a great one.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.2
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• pp.97-102
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• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• The Journal of Korean Association of Computer Education
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• v.7 no.2
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• pp.77-84
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• 2004

In this thesis, We propose the self-directed learning and test-performing abilities assessment method to evaluate the learning and the test-performing abilities in which learners can not only control their own learning abilities for themselves, but also judge objectively learning and test-performing abilities. This method shows the membership degree of learning and test-performing abilities by using both the triangle-type membership function and the fuzzy logic. In addition, it gives the fuzzy grades to each item. The final membership degrees are calculated and the fuzzy grades are decided by the operation and composition of fuzzy relations on the membership degrees of learning and test-performing abilities. In this method, which is applicable to a writing subject for information searchers, learners are asked to analyse the membership degrees of the learning and test-performing abilities and the final fuzzy grades and to adjust a learning process for themselves.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• Journal of the Korea Society of Computer and Information
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• v.25 no.11
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• pp.97-104
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• 2020

In this paper, we propose a random number generator PP(PingPong256) and a shuffle technique to improve the problem that the encrypted image is damaged due to a lot of noise by the channel coding of wireless communication recommended in the special environment of space. The PP can constantly generate random numbers by entering an initial value of 512 bits. Random numbers can be encrypted through images and exclusive logical computations. Random numbers can be encrypted through images and exclusive logical computations. The shuffle technique randomly rearranges the image pixel positions while synchronizing the image pixel position and the random number array position and moving the random number arrangement in ascending order. Therefore, the use of PP and shuffle techniques in channel coding allows all pixels to be finely distributed and transmit high-quality images even in poor transmission environments.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.20-29
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• 1998

This paper proposes the algorithms that design the highly parallel multiple-valued logic curcuit and assign the code to each node of DCG(Directed Cyclic Graph) of length 1. The conventional Nakajima's algorithm have some problems, so this paper introduce the matrix equation from DCG of length 1 and proposes circuit design algorithms according to the DCG of length 1. Using the proposed circuit design algorithms in this paper, it become realized that was not able to design from Nakajima's algorithm. Also, making a comparision between the circuit design using Nakajima's algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed curcuit design algorithm in this paper, it is possible to design curcuit that DCG have natural number, so it have the following advantages; reduction of the curcuit input/output digits, simplification of curcuit composition, reduction of computation time and cost. And we show compatibility and verification about this paper's algorithm.

• Journal of Korea Multimedia Society
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• v.1 no.1
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• pp.1-17
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• 1998

Video information is an important component of multimedia systems such as Digital Library, World-Wide Web (WWW), and Video-On-Demand (VOD) service system. Video information has hierarchical document structure inherently, so it is named "structure video document" in this paper. This paper proposes a data model, a query language, and an indexing scheme for structured video documents in order to store, retrieve, and share video documents efficiently. In representing structured video documents, the object-oriented data modeling technique is used since the hierarchical structure information can be modeled as complex objects. We also define object types for the structure information. Our query language supports not only content-based retrieval, which means the queries based on the structure of video documents, and spatial/temporal relation for video documents. In order to perform structure queries efficiently, as well as to reduce the storage overhead of indices, an optimized inverted index structure is proposed.

• Journal of Korea Multimedia Society
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• v.11 no.8
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• pp.1093-1100
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• 2008

Feistel and SPN are the two main structures in designing a block cipher algorithm. Unlike Feistel, an SPN has an asymmetric structure in encryption and decryption. In this paper we propose an SPN algorithm which has a symmetric structure in encryption and decryption. The whole operations in our SPN algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2, applies function and the last half of them, (N+1)/2 to N, employs inverse function. Symmetry layer is executed to create a symmetry block in between function layer and inverse function layer. AES encryption and decryption algorithm, whose safety is already proved, are exploited for function and inverse function, respectively. In order to be secure enough against the byte or word unit-based attacks, 32bit rotation and simple logical operations are performed in symmetry layer. Due to the simplicity of the proposed encryption and decryption algorithm in hardware configuration, the proposed algorithm is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.672-679
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• 2011

In this paper, detection algorithm of face region based on skin color of in the TV images is proposed. In the first, reference image is set to the sampled skin color, and then the extracted of face region is candidated using the Euclidean distance between the pixels of TV image. The eye image is detected by using the mean value and standard deviation of the component forming color difference between Y and C through the conversion of RGB color into CMY color model. Detecting the lips image is calculated by utilizing Q component through the conversion of RGB color model into YIQ color space. The detection of the face region is extracted using basis of knowledge by doing logical calculation of the eye image and lips image. To testify the proposed method, some experiments are performed using front color image down loaded from TV color image. Experimental results showed that face region can be detected in both case of the irrespective location & size of the human face.