• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1218-1226
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• 2008

With the development of semiconductor integrated technology and with the increasing use of multimedia functions in computer, more functions have been implemented as hardware. Nowadays, most microprocessors beyond 32 bits generally implement an integer multiplier as hardware. However, as for a divider, only specific microprocessor implements traditional SRT algorithm as hardware due to complexity of implementation and slow speed. This paper suggested an algorithm that uses a multiplier, 'w bit $\times$ w bit = 2w bit', to process $\frac{N}{D}$ integer division. That is, the reciprocal number D is first calculated, and then multiply dividend N to process integer division. In this paper, when the divisor D is '$D=0.d{\times}2^L$, 0.5 < 0.d < 1.0', approximate value of ' $\frac{1}{D}$', '$1.g{\times}2^{-L}$', which satisfies ' $0.d{\times}1.g=1+e$, $e<2^{-w}$', is defined as over reciprocal number and then an algorithm for over reciprocal number is suggested. This algorithm multiplies over reciprocal number '$01.g{\times}2^{-L}$' by dividend N to process $\frac{N}{D}$ integer division. The algorithm suggested in this paper doesn't require additional revision, because it can calculate correct reciprocal number. In addition, this algorithm uses only multiplier, so additional hardware for division is not required to implement microprocessor. Also, it shows faster speed than the conventional SRT algorithm and performs operation by word unit, accordingly it is more suitable to make compiler than the existing division algorithm. In conclusion, results from this study could be used widely for implementation SOC(System on Chip) and etc. which has been restricted to microprocessor and size of the hardware.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.3
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• pp.41-48
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• 2004

Finite field multiplication and division are important arithmetic operation in error-correcting codes and cryptosystems. The elements of the finite field GF($2^m$) are represented by bases with a primitive polynomial of degree m over GF(2). We can be easily realized for multiplication or computing multiplicative inverse in GF($2^m$) based on a normal basis representation. The number of product terms of logic function determines a complexity of the Messay-Omura multiplier. A normal basis exists for every finite field. It is not easy to find the optimal normal element for a given primitive polynomial. In this paper, the generating method of normal basis is investigated. The normal bases whose product terms are less than other bases for multiplication in GF($2^m$) are found. For each primitive polynomial, a list of normal elements and number of product terms are presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2253-2260
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• 2012

In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.1
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• pp.46-55
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• 2007

The Newton-Raphson's algorithm for finding a floating point reciprocal and inverse square root calculates the result by performing a fixed number of multiplications. In this paper, an improved Newton-Raphson's algorithm is proposed, that performs multiplications a variable number. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation is derived from many reciprocal and inverse square tables with varying sizes. The superiority of this algorithm is proved by comparing this average number with the fixed number of multiplications of the conventional algorithm. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a reciprocal and inverse square root unit. Also, it can be used to construct optimized approximate tables. The results of this paper can be applied to many areas that utilize floating point numbers, such as digital signal processing, computer graphics, multimedia, scientific computing, etc.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.292-295
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• 2003

블루투스 전송 기술은 2.4㎓ 의 ISM(Industrial Scientific Medicine)밴드에서 주파수 호핑 방식을 사용한다. 주파수 호핑율은 연결 상태에서 초당 1600회, 조회 또는 호출 상태에서 초당 3200회의 호핑을 한다. Hop 채널 선택은 블루투스 표준안에서 제시한 5개의 호핑 시퀸스 중 하나를 선택하고 호핑 주파수에 따라 이를 매핑 함으로써 이루어진다. 본 논문에서는 6개의 상태에 따라 다르게 실행되는 채널 계산을 효율적으로 제어하고 필요한 연산모듈의 수를 줄이기 위해 9비트 프로세서를 이용해 Hop 선택 모듈을 설계하고 구현한다. 설계된 모듈은 레지스터 파일, 마이크로프로그램 제어장치, 가산, 치환(permutation), Modulo 계산을 위한 3개의 연산장치로 구성된다. Hop 채널 계산 중 가장 클럭 소요가 큰 Modulo 연산은 SRT나눗셈 알고리즘을 사용하여 음수 값 계산 및 연산 속도 향상을 꾀하였다. 제시된 Hop 선택 모듈은 하드웨어 묘사언어인 VHDL로 설계하고 시뮬레이션 및 테스트는 Xilinx FPGA를 이용해 검증하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.1
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• pp.3-11
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• 2000

AAL-1에서는 (128, 124) Reed-Solomon부호를 사용한 인터리버 및 디인터리버에 의해 ATM 셀에서 발생하는 오류를 정정하고 있다. Reed-Solomon부호의 복호법 중 직접복호법은 오류위치다항식의 계산없이 오류위치와 오류치를 알 수 있으며 유한체 GF(2m)의 표현에서 정규기저를 사용하면 곱셈과 나눗셈을 단순한게 비트 이동만으로 처리할 수 있다. 직접복호법과 정규기저를 사용하여 ATM 적응계층에 적용 가능한 (128, 124) Reed-Solomon부호의 복호기를 설계하고 VHDL로 시뮬레이션 하였으며 이 복호기는 동일한 복호회로에 의해 둘 또는 하나의 심벌에 발생한 오류를 정정할 수 있다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.3
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• pp.185-191
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• 2022

This paper proposed a division algorithm of performance complexity $O{\frac{n(n+1)}{2}}$ for a change-making problem(CMP) in which polynomial time algorithms are not known as NP-hard problem. CMP seeks to minimize the sum of the x_j number of coins exchanged when a given amount of money C is exchanged for c_j,j=1,2,⋯,n coins. Known polynomial algorithms for CMPs are greedy algorithms(GA), divide-and-conquer (DC), and dynamic programming(DP). The optimal solution can be obtained by DP of O(nC), and in general, when given C>2ⁿ, the performance complexity tends to increase exponentially, so it cannot be called a polynomial algorithm. This paper proposes a simple algorithm that calculates quotient by dividing upper triangular matrices and main diagonal for k×n matrices in which only j columns are placed in descending order of c_j of n for c_j ≤ C and i rows are placed k excluding all the dividers in c_j. The application of the proposed algorithm to 39 benchmarking experimental data of various types showed that the optimal solution could be obtained quickly and accurately with only a calculator.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

• Journal of the Korean Chemical Society
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• v.47 no.1
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• pp.31-37
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• 2003

The expanded uncertainties calculated by the application of GUM -approximation and Monte-Carlo simulation were compared about the model equation of one-point calibration which is widely used for the measurements and chemical analysis. For the comparisons, we assumed a set of artificial data at the various level of concentration and dispersion of t or normal distribution. Mistakes of more then 50 % was revealed at the values calculated by GUM-approximation in comparison with those of Monte-Carlo simulation because of the excess dispersion from t-distribution and non-linearity by division in the equation. In contrary, the mistake of calculation due to non-linearity of the equation was not observed in the level of detection limits with the equation of one-point calibration, because of the relatively large values of uncertainty in response.

• School Mathematics
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• v.8 no.2
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• pp.139-160
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• 2006

It seems that North Korea has been trying to reorganize its educational system as well as its economic system on a large scale since July 1, 2002. There has been a decrease in quantity of math textbooks by about 30% decrease. Until the 1990's, geometry and algebra had been kept apart from each other in North Korea, but they are put together now. Moreover many changes have been made in both contents and methods of teaching. For example, an area model is used in North Korea to teach operation of fraction, which makes the learning period shorter. This idea will provide us with many implication when we need to ready for decreasing the quantities in the future. Moreover teaching methods of division algorithms need to be reconsidered since the visual algorithm of division could help save the thinking in problem solving.